PERFORCE change 211576 for review

[Robert Watson]

http://p4web.freebsd.org/@@211576?ac=10

Change 211576 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/05/23 13:24:48

	Allocate a CP2 register as 'udc' -- the user default data
	capability, which will hold the preserved userspace capability
	0 for restoration following lightweight exception handling that
	does not trigger a full context switch (e.g., TLB miss).

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#4 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#5 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#4 (text+ko) ====

@@ -184,8 +184,8 @@
 	CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c24);
 	CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c24);
 
-	CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c25);
-	CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c25);
+	CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_udc);
+	CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_udc);
 
 	CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_tsc);
 	CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_tsc);

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#5 (text+ko) ====

@@ -73,6 +73,7 @@
  */
 #define	CHERI_CR_C0	0	/*   MIPS fetch/load/store capability. */
 #define	CHERI_CR_CT0	10	/*   CT0: temporary capability. */
+#define	CHERI_CR_UDC	25	/*   SC0: user data capability. */
 #define	CHERI_CR_KT0	26	/*   KT0: temporary kernel capability. */
 #define	CHERI_CR_KT1	27	/*   KT1: temporary kernel capability. */
 #define	CHERI_CR_TSC	28	/*   TSC: trusted stack capability. */
@@ -116,17 +117,19 @@
 	struct capability	cf_c8, cf_c9, cf_c10, cf_c11, cf_c12;
 	struct capability	cf_c13, cf_c14, cf_c15, cf_c16, cf_c17;
 	struct capability	cf_c18, cf_c19, cf_c20, cf_c21, cf_c22;
-	struct capability	cf_c23, cf_c24, cf_c25;
+	struct capability	cf_c23, cf_c24;
 
 	/*
 	 * Special-purpose capability registers that must be preserved on a
 	 * user context switch.  Note that KT0, KT1, KCC, and KDC are omitted.
 	 */
+	struct capability	cf_udc;
 	struct capability	cf_tsc;
 
 	/* Program counter capability. */
 	struct capability	cf_pcc;
 };
+CTASSERT(sizeof(struct cp2_frame) == (28 * CAPABILITY_SIZE));
 
 /*
  * CP2 capability register manipulation macros.