PERFORCE change 206496 for review

[Robert Watson]

http://p4web.freebsd.org/@@206496?ac=10

Change 206496 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/02/18 13:31:53

	Don't issue the MIPS4k 'sync' instruction on non-SMP systems, since
	it probably isn't required ... and is currently missing from BERI,
	causing a reserved instruction exception early in boot.

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache_mipsNN.c#2 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache_mipsNN.c#2 (text+ko) ====

@@ -72,6 +72,7 @@
 }
 #endif
 
+#ifdef SMP
 #if defined(SB1250_PASS1)
 #define	SYNC	__asm volatile("sync; sync")
 #elif defined(CPU_NLM)
@@ -79,6 +80,9 @@
 #else
 #define	SYNC	__asm volatile("sync")
 #endif
+#else
+#define	SYNC
+#endif
 
 #if defined(CPU_CNMIPS)
 #define SYNCI  mips_sync_icache();