PERFORCE change 196806 for review
Jakub Wojciech Klama
jceel at FreeBSD.org
Thu Jul 28 00:44:35 UTC 2011
http://p4web.freebsd.org/@@196806?ac=10
Change 196806 by jceel at jceel_cyclone on 2011/07/28 00:43:41
* Add SSP/SPI bus driver
* Add SSD1289 LCD controller driver
* Fixes in GPIO driver
* Add framebuffer driver
* Insert LCD configuration into .dts file
Affected files ...
.. //depot/projects/soc2011/jceel_lpc/sys/arm/conf/EA3250#7 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/conf/EA3250.hints#1 add
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/files.lpc#6 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_fb.c#1 add
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_gpio.c#4 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_machdep.c#3 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_spi.c#1 add
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#6 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcvar.h#4 edit
.. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/ssd1289.c#1 add
.. //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#7 edit
Differences ...
==== //depot/projects/soc2011/jceel_lpc/sys/arm/conf/EA3250#7 (text+ko) ====
@@ -6,6 +6,7 @@
ident EA3250
include "../lpc/std.lpc"
+hints "EA3250.hints"
makeoptions MODULES_OVERRIDE=""
@@ -18,13 +19,13 @@
options FFS #Berkeley Fast Filesystem
options NFSCL #Network Filesystem Client
options NFSLOCKD #Network Lock Manager
-#options NFS_ROOT #NFS usable as /, requires NFSCLIENT
-#options BOOTP
-#options BOOTP_NFSROOT
-#options BOOTP_NFSV3
-#options BOOTP_WIRED_TO=lpe0
+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=lpe0
-options ROOTDEVNAME=\"ufs:/dev/da0a\"
+#options ROOTDEVNAME=\"ufs:/dev/da0a\"
#options MD_ROOT # MD is a potential root device
#options MD_ROOT_SIZE=8192 # 8MB ram disk
@@ -90,7 +91,11 @@
device gpioled
device lpcgpio
-#device lpcfb
+device spibus
+device lpcspi
+device ssd1289
+
+device lpcfb
# Flattened Device Tree
options FDT
==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/files.lpc#6 (text+ko) ====
@@ -12,7 +12,9 @@
arm/lpc/if_lpe.c optional lpe
arm/lpc/lpc_ohci.c optional ohci
arm/lpc/lpc_mmc.c optional lpcmmc
-#arm/lpc/lpc_fb.c optional lpcfb
+arm/lpc/lpc_fb.c optional lpcfb
arm/lpc/lpc_gpio.c optional lpcgpio
+arm/lpc/lpc_spi.c optional lpcspi
+arm/lpc/ssd1289.c optional ssd1289
dev/uart/uart_dev_ns8250.c optional uart
kern/kern_clocksource.c standard
==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_gpio.c#4 (text+ko) ====
@@ -78,6 +78,7 @@
#include <machine/resource.h>
#include <machine/frame.h>
#include <machine/intr.h>
+#include <machine/fdt.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
@@ -501,6 +502,17 @@
return lpc_gpio_pin_get(lpc_gpio_sc->lg_dev, pin, state);
}
+void
+platform_gpio_init()
+{
+ /* Preset SPI devices CS pins to one */
+ bus_space_write_4(fdtbus_bs_tag,
+ LPC_GPIO_BASE, LPC_GPIO_P3_OUTP_SET,
+ 1 << (SSD1289_CS_PIN - LPC_GPIO_GPO_00(0)) |
+ 1 << (SSD1289_DC_PIN - LPC_GPIO_GPO_00(0)) |
+ 1 << (ADS7846_CS_PIN - LPC_GPIO_GPO_00(0)));
+}
+
static device_method_t lpc_gpio_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, lpc_gpio_probe),
==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpc_machdep.c#3 (text+ko) ====
@@ -71,6 +71,7 @@
#include <dev/ofw/openfirm.h>
#include <arm/lpc/lpcreg.h>
+#include <arm/lpc/lpcvar.h>
#include <vm/vm.h>
#include <vm/pmap.h>
@@ -624,6 +625,11 @@
*/
physmap_init();
+ /*
+ * Set initial values of GPIO output ports
+ */
+ platform_gpio_init();
+
/* Do basic tuning, hz etc */
init_param2(physmem);
kdb_init();
==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#6 (text+ko) ====
@@ -144,6 +144,14 @@
#define LPC_CLKPWR_FLASHCLK_CTRL 0xc8
#define LPC_CLKPWR_MACCLK_CTRL 0x90
#define LPC_CLKPWR_LCDCLK_CTRL 0x54
+#define LPC_CLKPWR_LCDCLK_CTRL_DISPTYPE (1 << 8)
+#define LPC_CLKPWR_LCDCLK_CTRL_MODE(_n) ((_n & 0x3) << 6)
+#define LPC_CLKPWR_LCDCLK_CTRL_MODE_12 0x0
+#define LPC_CLKPWR_LCDCLK_CTRL_MODE_15 0x1
+#define LPC_CLKPWR_LCDCLK_CTRL_MODE_16 0x2
+#define LPC_CLKPWR_LCDCLK_CTRL_MODE_24 0x3
+#define LPC_CLKPWR_LCDCLK_CTRL_HCLKEN (1 << 5)
+#define LPC_CLKPWR_LCDCLK_CTRL_CLKDIV(_n) ((_n) & 0x1f)
#define LPC_CLKPWR_I2S_CTRL 0x7c
#define LPC_CLKPWR_SSP_CTRL 0x78
#define LPC_CLKPWR_SSP_CTRL_SSP1RXDMA (1 << 5)
@@ -351,12 +359,52 @@
* LCD Controller (from UM10326: LPC32x0 User manual, page 229)
*/
#define LPC_LCD_TIMH 0x00
+#define LPC_LCD_TIMH_HBP(_n) (((_n) & 0xff) << 24)
+#define LPC_LCD_TIMH_HFP(_n) (((_n) & 0xff) << 16)
+#define LPC_LCD_TIMH_HSW(_n) (((_n) & 0xff) << 8)
+#define LPC_LCD_TIMH_PPL(_n) (((_n) / 16 - 1) << 2)
#define LPC_LCD_TIMV 0x04
+#define LPC_LCD_TIMV_VBP(_n) (((_n) & 0xff) << 24)
+#define LPC_LCD_TIMV_VFP(_n) (((_n) & 0xff) << 16)
+#define LPC_LCD_TIMV_VSW(_n) (((_n) & 0x3f) << 10)
+#define LPC_LCD_TIMV_LPP(_n) ((_n) & 0x1ff)
#define LPC_LCD_POL 0x08
+#define LPC_LCD_POL_PCD_HI (((_n) & 0x1f) << 27)
+#define LPC_LCD_POL_BCD (1 << 26)
+#define LPC_LCD_POL_CPL(_n) (((_n) & 0x3ff) << 16)
+#define LPC_LCD_POL_IOE (1 << 14)
+#define LPC_LCD_POL_IPC (1 << 13)
+#define LPC_LCD_POL_IHS (1 << 12)
+#define LPC_LCD_POL_IVS (1 << 11)
+#define LPC_LCD_POL_ACB(_n) ((_n & 0x1f) << 6)
+#define LPC_LCD_POL_CLKSEL (1 << 5)
+#define LPC_LCD_POL_PCD_LO(_n) ((_n) & 0x1f)
#define LPC_LCD_LE 0x0c
+#define LPC_LCD_LE_LEE (1 << 16)
+#define LPC_LCD_LE_LED ((_n) & 0x7f)
#define LPC_LCD_UPBASE 0x10
#define LPC_LCD_LPBASE 0x14
#define LPC_LCD_CTRL 0x18
+#define LPC_LCD_CTRL_WATERMARK (1 << 16)
+#define LPC_LCD_CTRL_LCDVCOMP(_n) (((_n) & 0x3) << 12)
+#define LPC_LCD_CTRL_LCDPWR (1 << 11)
+#define LPC_LCD_CTRL_BEPO (1 << 10)
+#define LPC_LCD_CTRL_BEBO (1 << 9)
+#define LPC_LCD_CTRL_BGR (1 << 8)
+#define LPC_LCD_CTRL_LCDDUAL (1 << 7)
+#define LPC_LCD_CTRL_LCDMONO8 (1 << 6)
+#define LPC_LCD_CTRL_LCDTFT (1 << 5)
+#define LPC_LCD_CTRL_LCDBW (1 << 4)
+#define LPC_LCD_CTRL_LCDBPP(_n) (((_n) & 0x7) << 1)
+#define LPC_LCD_CTRL_BPP1 0
+#define LPC_LCD_CTRL_BPP2 1
+#define LPC_LCD_CTRL_BPP4 2
+#define LPC_LCD_CTRL_BPP8 3
+#define LPC_LCD_CTRL_BPP16 4
+#define LPC_LCD_CTRL_BPP24 5
+#define LPC_LCD_CTRL_BPP16_565 6
+#define LPC_LCD_CTRL_BPP12_444 7
+#define LPC_LCD_CTRL_LCDEN (1 << 0)
#define LPC_LCD_INTMSK 0x1c
#define LPC_LCD_INTRAW 0x20
#define LPC_LCD_INTSTAT 0x24
@@ -453,6 +501,7 @@
/*
* GPIO (from UM10326: LPC32x0 User manual, page 606)
*/
+#define LPC_GPIO_BASE (LPC_DEV_BASE + 0x28000)
#define LPC_GPIO_P0_COUNT 8
#define LPC_GPIO_P1_COUNT 24
#define LPC_GPIO_P2_COUNT 13
@@ -488,6 +537,11 @@
#define LPC_GPIO_GPI_27(_n) (20 + _n)
#define LPC_GPIO_GPO_00(_n) (22 + _n)
#define LPC_GPIO_GPIO_00(_n) (46 + _n)
+/* SPI devices chip selects: */
+#define SSD1289_CS_PIN LPC_GPIO_GPO_00(4)
+#define SSD1289_DC_PIN LPC_GPIO_GPO_00(5)
+#define ADS7846_CS_PIN LPC_GPIO_GPO_00(11)
+#define ADS7846_INTR_PIN LPC_GPIO_GPIO_00(0)
/*
* GPDMA controller (from UM10326: LPC32x0 User manual, page 106)
==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcvar.h#4 (text+ko) ====
@@ -36,8 +36,24 @@
void lpc_pwr_write(device_t, int, uint32_t);
/* GPIO */
+void platform_gpio_init(void);
int lpc_gpio_set_flags(device_t, int, int);
int lpc_gpio_set_state(device_t, int, int);
int lpc_gpio_get_state(device_t, int, int *);
+/* DMA */
+struct lpc_dmac_channel_config
+{
+ int ldc_src_periph;
+ int ldc_dst_periph;
+ int ldc_src_width;
+ int ldc_dst_width;
+ void (*ldc_success_handler)(void);
+ void (*ldc_error_handler)(void);
+};
+
+int lpc_dmac_config_channel(device_t, int, struct lpc_dmac_channel_config *);
+int lpc_dmac_setup_transfer(device_t, int, bus_addr_t, bus_addr_t, bus_size_t, int);
+int lpc_dmac_enable_transfer(device_t, int);
+
#endif /* _ARM_LPC_LPCVAR_H */
==== //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#7 (text+ko) ====
@@ -191,6 +191,19 @@
reg = <0x1040000 0x20000>;
interrupts = <14>;
interrupt-parent = <&PIC>;
+
+ /* Screen parameters: */
+ is-tft = <1>;
+ horizontal-resolution = <240>;
+ vertical-resolution = <320>;
+ bits-per-pixel = <16>;
+ pixel-clock = <121654>;
+ left-margin = <28>;
+ right-margin = <10>;
+ upper-margin = <2>;
+ lower-margin = <2>;
+ hsync-len = <3>;
+ vsync-len = <2>;
};
lpe at 1060000 {
@@ -218,6 +231,21 @@
compatible = "simple-bus";
ranges = <0x0 0x20000000 0x10000000>;
+ spi0 at 84000 {
+ compatible = "lpc,spi";
+ reg = <0x84000 0x4000>;
+ interrupts = <20>;
+ interrupt-parent = <&PIC>;
+ };
+
+ spi1 at 8c000 {
+ compatible = "lpc,spi";
+ status = "disabled";
+ reg = <0x8c000 0x4000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+
lpcmmc at 98000 {
compatible = "lpc,mmc";
reg = <0x98000 0x4000>;
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