PERFORCE change 175747 for review

[Rafal Jaworowski]

http://p4web.freebsd.org/chv.cgi?CH=175747

Change 175747 by raj at raj_fdt on 2010/03/16 21:31:12

	Clean up DB-78XXX for FDT support.

Affected files ...

.. //depot/projects/fdt/sys/arm/mv/discovery/db78xxx.c#2 edit
.. //depot/projects/fdt/sys/arm/mv/discovery/discovery.c#2 edit

Differences ...

==== //depot/projects/fdt/sys/arm/mv/discovery/db78xxx.c#2 (text+ko) ====

@@ -102,52 +102,6 @@
 	{ -1, -1, -1 }
 };
 
-void
-platform_mpp_init(void)
-{
-
-	/*
-	 * MPP Configuration for DB-78100-BP
-	 *
-	 * MPP[0]:  GE1_TXCLK
-	 * MPP[1]:  GE1_TXCTL
-	 * MPP[2]:  GE1_RXCTL
-	 * MPP[3]:  GE1_RXCLK
-	 * MPP[4]:  GE1_TXD[0]
-	 * MPP[5]:  GE1_TXD[1]
-	 * MPP[6]:  GE1_TXD[2]
-	 * MPP[7]:  GE1_TXD[3]
-	 * MPP[8]:  GE1_RXD[0]
-	 * MPP[9]:  GE1_RXD[1]
-	 * MPP[10]: GE1_RXD[2]
-	 * MPP[11]: GE1_RXD[3]
-	 * MPP[13]: SYSRST_OUTn
-	 * MPP[14]: SATA1_ACT
-	 * MPP[15]: SATA0_ACT
-	 * MPP[16]: UA2_TXD
-	 * MPP[17]: UA2_RXD
-	 * MPP[18]: <UNKNOWN>
-	 * MPP[19]: <UNKNOWN>
-	 * MPP[20]: <UNKNOWN>
-	 * MPP[21]: <UNKNOWN>
-	 * MPP[22]: UA3_TXD
-	 * MPP[23]: UA3_RXD
-	 * MPP[48]: <UNKNOWN>
-	 * MPP[49]: <UNKNOWN>
-	 *
-	 * Others:  GPIO
-	 *
-	 * <UNKNOWN> entries are not documented, not on the schematics etc.
-	 */
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x22222222);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x33302222);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x44333344);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL3, 0x00000000);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL4, 0x00000000);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL5, 0x00000000);
-	bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL6, 0x0000FFFF);
-}
-
 static void
 platform_identify(void *dummy)
 {

==== //depot/projects/fdt/sys/arm/mv/discovery/discovery.c#2 (text+ko) ====

@@ -60,88 +60,6 @@
  * is better and flexible to instantiate the number of PCI bridge devices
  * (known in run-time) in the pcib_mbus_identify() method.
  */
-struct obio_device obio_devices[] = {
-	{ "ic", MV_IC_BASE, MV_IC_SIZE,
-		{ -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
-		{ MV_INT_TIMER0, -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
-		{ MV_INT_GPIO7_0, MV_INT_GPIO15_8,
-		  MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "uart", MV_UART0_BASE, MV_UART_SIZE,
-		{ MV_INT_UART0, -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "uart", MV_UART1_BASE, MV_UART_SIZE,
-		{ MV_INT_UART1, -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "idma", MV_IDMA_BASE, MV_IDMA_SIZE,
-		{ MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1,
-		  MV_INT_IDMA2, MV_INT_IDMA3, -1 },
-		{ -1 },
-		CPU_PM_CTRL_IDMA
-	},
-	{ "xor", MV_XOR_BASE, MV_XOR_SIZE,
-		{ MV_INT_XOR0, MV_INT_XOR1,
-		  MV_INT_XOR_ERR, -1 },
-		{ -1 },
-		CPU_PM_CTRL_XOR
-	},
-	{ "ehci", MV_USB0_BASE, MV_USB_SIZE,
-		{ MV_INT_USB_ERR, MV_INT_USB0, -1 },
-		{ -1 },
-		CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2
-	},
-	{ "ehci", MV_USB1_BASE, MV_USB_SIZE,
-		{ MV_INT_USB_ERR, MV_INT_USB1, -1 },
-		{ -1 },
-		CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2
-	},
-	{ "ehci", MV_USB2_BASE, MV_USB_SIZE,
-		{ MV_INT_USB_ERR, MV_INT_USB2, -1 },
-		{ -1 },
-		CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2
-	},
-	{ "mge", MV_ETH0_BASE, MV_ETH_SIZE,
-		{ MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
-		  MV_INT_GBESUM, MV_INT_GBE_ERR, -1 },
-		{ -1 },
-		CPU_PM_CTRL_GE0
-	},
-	{ "mge", MV_ETH1_BASE, MV_ETH_SIZE,
-		{ MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC,
-		  MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 },
-		{ -1 },
-		CPU_PM_CTRL_GE1
-	},
-	{ "twsi", MV_TWSI0_BASE, MV_TWSI_SIZE,
-		{ -1 }, { -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "twsi", MV_TWSI1_BASE, MV_TWSI_SIZE,
-		{ -1 }, { -1 },
-		CPU_PM_CTRL_NONE
-	},
-	{ "sata", MV_SATAHC_BASE, MV_SATAHC_SIZE,
-		{ MV_INT_SATA, -1 },
-		{ -1 },
-		CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1
-	},
-	{ NULL, 0, 0, { 0 }, { 0 }, 0 }
-};
-
 const struct obio_pci mv_pci_info[] = {
 	{ MV_TYPE_PCIE,
 		MV_PCIE00_BASE, MV_PCIE_SIZE,
@@ -214,25 +132,6 @@
 	{ -1, 0 }
 };
 
-const struct decode_win cpu_win_tbl[] = {
-	/* Device bus BOOT */
-	{ 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
-
-	/* Device bus CS0 */
-	{ 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
-
-	/* Device bus CS1 */
-	{ 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
-
-	/* Device bus CS2 */
-	{ 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
-
-	/* CESA */
-	{ 9, 0x01, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 },
-};
-const struct decode_win *cpu_wins = cpu_win_tbl;
-int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
-
 /*
  * Note: the decode windows table for IDMA does not explicitly have DRAM
  * entries, which are not statically defined: active DDR banks (== windows)