PERFORCE change 180415 for review
Volodymyr Serbinenko
phcoder at FreeBSD.org
Fri Jul 2 14:51:28 UTC 2010
http://p4web.freebsd.org/@@180415?ac=10
Change 180415 by phcoder at phcoder_ on 2010/07/02 14:50:59
Resync with bzr. Now USB works but only when debug messages are enabled and only the controller on PCI (no Geode yet)
Affected files ...
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/conf/YEELOONG#3 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpuregs.h#4 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/busdma_machdep.c#3 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/exception.S#4 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/locore.S#4 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/pmap.c#3 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/bonito_pci.c#1 add
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/files.yeeloong#2 edit
.. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/yeeloong_machdep.c#3 edit
Differences ...
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/conf/YEELOONG#3 (text+ko) ====
@@ -41,8 +41,22 @@
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+options USB_DEBUG # enable debug msgs
device loop
device ether
device md
device uart
+
+options MSDOSFS # MSDOS Filesystem
+options CD9660 # ISO 9660 Filesystem
+options PROCFS # Process filesystem (requires PSEUDOFS)
+options GEOM_PART_GPT # GUID Partition Tables.
+options GEOM_LABEL # Provides labelization
+
+device ch # SCSI media changers
+device da # Direct Access (disks)
+device sa # Sequential Access (tape etc)
+device cd # CD
+device pass # Passthrough device (direct SCSI access)
+device ses # SCSI Environmental Services (and SAF-TE)
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpuregs.h#4 (text+ko) ====
@@ -100,7 +100,7 @@
#define MIPS_XKPHYS_CCA_CNC 0x03 /* Cacheable non-coherent. */
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
- ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
+ ((0x2ULL << 62) | ((unsigned long long)(2) << 59) | (x))
#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x07ffffffffffffffULL)
#define MIPS_XUSEG_START 0x0000000000000000
@@ -343,7 +343,7 @@
#define MIPS_VEC_EJTAG 0xBFC00480
#define MIPS_VEC_TLB 0x80000000
#define MIPS_VEC_XTLB 0x80000080
-#define MIPS_VEC_CACHE 0x80000100
+#define MIPS_VEC_CACHE 0xa0000100
#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */
#define MIPS_VEC_INTERRUPT 0x80000200
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/busdma_machdep.c#3 (text+ko) ====
@@ -805,6 +805,9 @@
if (++seg >= dmat->nsegments)
break;
segs[seg].ds_addr = curaddr;
+#ifdef TARGET_YEELOONG
+ segs[seg].ds_addr |= 0x80000000;
+#endif
segs[seg].ds_len = sgsize;
}
if (error)
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/exception.S#4 (text+ko) ====
@@ -156,7 +156,10 @@
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded
COP0_SYNC
+ MTC0 zero, COP_0_TLB_PG_MASK
+ COP0_SYNC
tlbwr #1a: write to tlb
+
HAZARD_DELAY
eret #1f: retUrn from exception
1: j MipsTLBMissException #20: kernel exception
@@ -851,7 +854,10 @@
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1
COP0_SYNC
+ MTC0 zero, COP_0_TLB_PG_MASK
+ COP0_SYNC
+
b tlb_insert_entry
nop
@@ -864,6 +870,8 @@
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1
COP0_SYNC
+ MTC0 zero, COP_0_TLB_PG_MASK
+ COP0_SYNC
tlb_insert_entry:
tlbp
@@ -1006,6 +1014,8 @@
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded
COP0_SYNC
+ MTC0 zero, COP_0_TLB_PG_MASK
+ COP0_SYNC
tlbwr # write to tlb
HAZARD_DELAY
eret # return from exception
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/locore.S#4 (text+ko) ====
@@ -158,9 +158,48 @@
mtc0 t2, COP_0_STATUS_REG
COP0_SYNC
+ lui t0, 0x8000
+ lui t1, 0x8000
+ addiu t1, 0x4000
+1:
+ cache 0, 0(t0)
+ cache 0, 1(t0)
+ cache 0, 2(t0)
+ cache 0, 3(t0)
+ addiu t0, 32
+ bne t0, t1, 1b
+ nop
+
+ lui t0, 0x8000
+ lui t1, 0x8000
+ addiu t1, 0x4000
+1:
+ cache 1, 0(t0)
+ cache 1, 1(t0)
+ cache 1, 2(t0)
+ cache 1, 3(t0)
+ addiu t0, 32
+ bne t0, t1, 1b
+ nop
+
+ lui t0, 0x8000
+ lui t1, 0x8002
+1:
+ cache 3, 0(t0)
+ cache 3, 1(t0)
+ cache 3, 2(t0)
+ cache 3, 3(t0)
+ addiu t0, 32
+ bne t0, t1, 1b
+ nop
+
+
/* Make sure KSEG0 is cached */
mfc0 t0, MIPS_COP_0_CONFIG
- ori t0, CFG_K0_CACHED
+ srl t0, 3
+ sll t0, 3
+ ori t0, 2
+// ori t0, CFG_K0_CACHED
mtc0 t0, MIPS_COP_0_CONFIG
COP0_SYNC
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/pmap.c#3 (text+ko) ====
@@ -226,7 +226,7 @@
sysm = &sysmap_lmem[cpu]; \
va = sysm->base; \
npte = TLBLO_PA_TO_PFN(phys) | \
- PG_D | PG_V | PG_G | PG_W | PG_C_CNC; \
+ PG_D | PG_V | PG_G | PG_W | PG_C_UC; \
pte = pmap_pte(kernel_pmap, va); \
*pte = npte; \
sysm->valid1 = 1
@@ -242,11 +242,11 @@
va1 = sysm->base; \
va2 = sysm->base + PAGE_SIZE; \
npte = TLBLO_PA_TO_PFN(phys1) | \
- PG_D | PG_V | PG_G | PG_W | PG_C_CNC; \
+ PG_D | PG_V | PG_G | PG_W | PG_C_UC; \
pte = pmap_pte(kernel_pmap, va1); \
*pte = npte; \
npte = TLBLO_PA_TO_PFN(phys2) | \
- PG_D | PG_V | PG_G | PG_W | PG_C_CNC; \
+ PG_D | PG_V | PG_G | PG_W | PG_C_UC; \
pte = pmap_pte(kernel_pmap, va2); \
*pte = npte; \
sysm->valid1 = 1; \
@@ -731,7 +731,7 @@
npte = TLBLO_PA_TO_PFN(pa) | PG_D | PG_V | PG_G | PG_W;
if (is_cacheable_mem(pa))
- npte |= PG_C_CNC;
+ npte |= PG_C_UC;
else
npte |= PG_C_UC;
@@ -1828,7 +1828,7 @@
newpte = TLBLO_PA_TO_PFN(pa) | rw | PG_V;
if (is_cacheable_mem(pa))
- newpte |= PG_C_CNC;
+ newpte |= PG_C_UC;
else
newpte |= PG_C_UC;
@@ -1990,7 +1990,7 @@
*pte = TLBLO_PA_TO_PFN(pa) | PG_V;
if (is_cacheable_mem(pa))
- *pte |= PG_C_CNC;
+ *pte |= PG_C_UC;
else
*pte |= PG_C_UC;
@@ -2045,7 +2045,7 @@
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
/* Since this is for the debugger, no locks or any other fun */
- npte = TLBLO_PA_TO_PFN(pa) | PG_D | PG_V | PG_G | PG_W | PG_C_CNC;
+ npte = TLBLO_PA_TO_PFN(pa) | PG_D | PG_V | PG_G | PG_W | PG_C_UC;
pte = pmap_pte(kernel_pmap, sysm->base);
*pte = npte;
sysm->valid1 = 1;
@@ -2939,20 +2939,20 @@
pt_entry_t rw;
if (!(prot & VM_PROT_WRITE))
- rw = PG_V | PG_RO | PG_C_CNC;
+ rw = PG_V | PG_RO | PG_C_UC;
else {
if (va >= VM_MIN_KERNEL_ADDRESS) {
/*
* Don't bother to trap on kernel writes, just
* record page as dirty.
*/
- rw = PG_V | PG_D | PG_C_CNC;
+ rw = PG_V | PG_D | PG_C_UC;
vm_page_dirty(m);
} else if ((m->md.pv_flags & PV_TABLE_MOD) ||
m->dirty == VM_PAGE_BITS_ALL)
- rw = PG_V | PG_D | PG_C_CNC;
+ rw = PG_V | PG_D | PG_C_UC;
else
- rw = PG_V | PG_C_CNC;
+ rw = PG_V | PG_C_UC;
vm_page_flag_set(m, PG_WRITEABLE);
}
return rw;
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/files.yeeloong#2 (text+ko) ====
@@ -4,3 +4,4 @@
mips/yeeloong/yeeloong_machdep.c standard
mips/mips/tick.c standard
mips/mips/intr_machdep.c standard
+mips/yeeloong/bonito_pci.c optional pci
==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/yeeloong_machdep.c#3 (text+ko) ====
@@ -81,12 +81,11 @@
printf("entry: mips_init()\n");
- memstart = 64 << 20; //(((vm_offset_t)&end) & 0x1fffffff);
-// memstart = (memstart + 2 * 1048576) & ~1048575;
+ memstart = ((((vm_offset_t)&end) + 0xfffff) & 0x1ff00000);
bootverbose = 1;
/* FIXME: retrieve memory map from loader. */
- realmem = btoc((32 << 20));
+ realmem = btoc((64 << 20) - memstart);
for (i = 0; i < 10; i++) {
phys_avail[i] = 0;
@@ -94,7 +93,7 @@
/* phys_avail regions are in bytes */
phys_avail[0] = memstart;
- phys_avail[1] = 96 << 20;
+ phys_avail[1] = (64 << 20);
physmem = realmem;
@@ -157,9 +156,6 @@
/* FIXME: retrieve from multiboot2 info. */
uint64_t platform_counter_freq = 400 * 1000 * 1000;
- *((volatile uint32_t *)(intptr_t) (int32_t) 0xbfe00150) = 0;
- *((volatile uint32_t *)(intptr_t) (int32_t) 0xbfe00154) = 0;
-
/* clear the BSS and SBSS segments */
kernend = round_page((vm_offset_t)&end);
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
@@ -170,6 +166,7 @@
boothowto = RB_MULTIPLE | RB_SERIAL;
cninit();
+
mips_init();
mips_timer_init_params(platform_counter_freq, 0);
}
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