PERFORCE change 176892 for review

[Rafal Jaworowski]

http://p4web.freebsd.org/@@176892?ac=10

Change 176892 by raj at raj_fdt on 2010/04/14 11:23:50

	Clean up PCI-Express regs definitions and usage.
	
	LTSSM is MPC85XX PCI-E specific, so make it local to the pcib back-end
	driver.
	
	Pointed out by:	jhb

Affected files ...

.. //depot/projects/fdt/sys/dev/pci/pcireg.h#4 edit
.. //depot/projects/fdt/sys/powerpc/mpc85xx/pci_fdt.c#4 edit

Differences ...

==== //depot/projects/fdt/sys/dev/pci/pcireg.h#4 (text+ko) ====

@@ -218,17 +218,6 @@
 
 #define	PCIR_PCCARDIF_2	0x44
 
-
-/* PCIE registers */
-#define PCIR_DCR	0x54
-#define PCIM_DCR_URR	0x0008
-#define PCIM_DCR_FER	0x0004
-#define PCIM_DCR_NFER	0x0002
-#define PCIR_DSR	0x56
-#define PCIR_LTSSM	0x404
-#define PCIM_LTSSM_L0	0x16
-
-
 /* PCI device class, subclass and programming interface definitions */
 
 #define	PCIC_OLD	0x00
@@ -616,6 +605,9 @@
 #define	PCIR_EXPRESS_DEVICE_CAP	0x4
 #define	PCIM_EXP_CAP_MAX_PAYLOAD	0x0007
 #define	PCIR_EXPRESS_DEVICE_CTL	0x8
+#define	PCIM_EXP_CTL_NFER_ENABLE	0x0002
+#define	PCIM_EXP_CTL_FER_ENABLE		0x0004
+#define	PCIM_EXP_CTL_URR_ENABLE		0x0008
 #define	PCIM_EXP_CTL_RELAXED_ORD_ENABLE	0x0010
 #define	PCIM_EXP_CTL_MAX_PAYLOAD	0x00e0
 #define	PCIM_EXP_CTL_NOSNOOP_ENABLE	0x0800

==== //depot/projects/fdt/sys/powerpc/mpc85xx/pci_fdt.c#4 (text+ko) ====

@@ -90,6 +90,9 @@
 #define	REG_PEX_ERR_DR	0x0e00
 #define	REG_PEX_ERR_EN	0x0e08
 
+#define PCIR_LTSSM	0x404
+#define LTSSM_STAT_L0	0x16
+
 #define	DEVFN(b, s, f)	((b << 16) | (s << 8) | f)
 
 struct fsl_pcib_softc {
@@ -113,6 +116,7 @@
 
 	int		sc_busnr;
 	int		sc_pcie;
+	uint8_t		sc_pcie_capreg;		/* PCI-E Capability Reg Set */
 
 	/* Devices that need special attention. */
 	int		sc_devfn_tundra;
@@ -236,8 +240,7 @@
 	phandle_t node;
 	uint32_t cfgreg;
 	int maxslot, subbus;
-	uint8_t ltssm;
-	uint8_t capptr;
+	uint8_t ltssm, capptr;
 
 	sc = device_get_softc(dev);
 	sc->sc_dev = dev;
@@ -270,6 +273,7 @@
 			break;
 		case PCIY_EXPRESS:
 			sc->sc_pcie = 1;
+			sc->sc_pcie_capreg = capptr;
 			break;
 		}
 		capptr = (cfgreg >> 8) & 0xff;
@@ -318,7 +322,7 @@
 
 	if (sc->sc_pcie) {
 		ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
-		if (ltssm < PCIM_LTSSM_L0) {
+		if (ltssm < LTSSM_STAT_L0) {
 			if (bootverbose)
 				printf("PCI %d: no PCIE link, skipping\n",
 				    device_get_unit(dev));
@@ -885,18 +889,25 @@
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
 		    0xffffffff);
 
-		dsr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_DSR, 2);
+		dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
+		    sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 2);
 		if (dsr)
-			fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_DSR, 0xffff, 2);
+			fsl_pcib_cfgwrite(sc, 0, 0, 0,
+			    sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA,
+			    0xffff, 2);
 
 		/* Enable all errors reporting */
 		err_en = 0x00bfff00;
-		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, err_en);
+		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
+		    err_en);
 
 		/* Enable error reporting: URR, FER, NFER */
-		dcr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_DCR, 4);
-		dcr |= PCIM_DCR_URR | PCIM_DCR_FER | PCIM_DCR_NFER;
-		fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_DCR, dcr, 4);
+		dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
+		    sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, 4);
+		dcr |= PCIM_EXP_CTL_URR_ENABLE | PCIM_EXP_CTL_FER_ENABLE |
+		    PCIM_EXP_CTL_NFER_ENABLE;
+		fsl_pcib_cfgwrite(sc, 0, 0, 0,
+		    sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, dcr, 4);
 	}
 }