PERFORCE change 176862 for review
Rafal Jaworowski
raj at FreeBSD.org
Tue Apr 13 15:14:50 UTC 2010
http://p4web.freebsd.org/@@176862?ac=10
Change 176862 by raj at raj_fdt on 2010/04/13 15:13:54
Clean up.
Affected files ...
.. //depot/projects/fdt/sys/arm/include/fdt.h#5 edit
.. //depot/projects/fdt/sys/arm/mv/bus_space.c#2 edit
.. //depot/projects/fdt/sys/arm/mv/discovery/discovery.c#4 edit
.. //depot/projects/fdt/sys/arm/mv/kirkwood/kirkwood.c#10 edit
.. //depot/projects/fdt/sys/arm/mv/mv_pci.c#3 edit
.. //depot/projects/fdt/sys/arm/mv/mvvar.h#8 edit
.. //depot/projects/fdt/sys/arm/mv/orion/orion.c#5 edit
Differences ...
==== //depot/projects/fdt/sys/arm/include/fdt.h#5 (text+ko) ====
@@ -55,7 +55,7 @@
/*
* Bus space tag. XXX endianess info needs to be derived from the blob.
*/
-#define fdtbus_bs_tag obio_tag
+extern bus_space_tag_t fdtbus_bs_tag;
struct mem_region {
vm_offset_t mr_start;
==== //depot/projects/fdt/sys/arm/mv/bus_space.c#2 (text+ko) ====
@@ -49,7 +49,7 @@
bs_protos(generic_armv4);
/*
- * The obio bus space tag. This is constant for all instances, so
+ * The bus space tag. This is constant for all instances, so
* we never have to explicitly "create" it.
*/
static struct bus_space _base_tag = {
@@ -159,4 +159,4 @@
NULL
};
-bus_space_tag_t obio_tag = &_base_tag;
+bus_space_tag_t fdtbus_bs_tag = &_base_tag;
==== //depot/projects/fdt/sys/arm/mv/discovery/discovery.c#4 (text+ko) ====
@@ -37,86 +37,12 @@
#include <sys/bus.h>
#include <machine/bus.h>
+#include <machine/fdt.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
#include <arm/mv/mvwin.h>
-#define _MV_PCIE_MAX_PORT 8
-
-#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT)
-#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT)
-
-#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE))
-#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE))
-
-#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE))
-#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE))
-
-#if 0
-/*
- * Note the 'pcib' devices are not declared in the obio_devices[]: due to the
- * much more complex configuration schemes allowed, specifically of the
- * PCI-Express (multiple lanes width per port configured dynamically etc.) it
- * is better and flexible to instantiate the number of PCI bridge devices
- * (known in run-time) in the pcib_mbus_identify() method.
- */
-const struct obio_pci mv_pci_info[] = {
- { MV_TYPE_PCIE,
- MV_PCIE00_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0,
- _MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8,
- NULL, MV_INT_PEX00 },
-
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE01_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0,
- _MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8,
- NULL, MV_INT_PEX01 },
-#if 0
- /*
- * XXX Access to devices on this interface (PCIE 0.2) crashes the
- * system. Could be a silicon defect as Marvell U-Boot has a 'Do not
- * touch' precaution comment...
- */
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE02_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0,
- _MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8,
- NULL, MV_INT_PEX02 },
-#endif
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE03_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70,
- _MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78,
- NULL, MV_INT_PEX03 },
-
- { MV_TYPE_PCIE,
- MV_PCIE10_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0,
- _MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8,
- NULL, MV_INT_PEX10 },
-
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE11_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0,
- _MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8,
- NULL, MV_INT_PEX11 },
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE12_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0,
- _MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8,
- NULL, MV_INT_PEX12 },
- { MV_TYPE_PCIE_AGGR_LANE,
- MV_PCIE13_BASE, MV_PCIE_SIZE,
- _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70,
- _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78,
- NULL, MV_INT_PEX13 },
-
- { 0, 0, 0 }
-};
-#endif
-
struct resource_spec mv_gpio_res[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
@@ -126,38 +52,17 @@
{ -1, 0 }
};
-struct resource_spec mv_xor_res[] = {
- { SYS_RES_MEMORY, 0, RF_ACTIVE },
- { SYS_RES_IRQ, 0, RF_ACTIVE },
- { SYS_RES_IRQ, 1, RF_ACTIVE },
- { SYS_RES_IRQ, 2, RF_ACTIVE },
- { -1, 0 }
-};
-
-/*
- * Note: the decode windows table for IDMA does not explicitly have DRAM
- * entries, which are not statically defined: active DDR banks (== windows)
- * are established in run time from actual DDR windows settings. All active
- * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
- * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
- * DDR banks are active, the remaining available IDMA decode windows for other
- * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
- */
const struct decode_win idma_win_tbl[] = {
- /* PCIE MEM */
- { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 },
- { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 },
+ { 0 },
};
const struct decode_win *idma_wins = idma_win_tbl;
-int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
+int idma_wins_no = 0;
const struct decode_win xor_win_tbl[] = {
- /* PCIE MEM */
- { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1},
- { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1},
+ { 0 },
};
const struct decode_win *xor_wins = xor_win_tbl;
-int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win);
+int xor_wins_no = 0;
uint32_t
get_tclk(void)
@@ -168,7 +73,7 @@
* On Discovery TCLK is can be configured to 166 MHz or 200 MHz.
* Current setting is read from Sample At Reset register.
*/
- sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI);
+ sar = bus_space_read_4(fdtbus_bs_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI);
sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
switch (sar) {
==== //depot/projects/fdt/sys/arm/mv/kirkwood/kirkwood.c#10 (text+ko) ====
@@ -54,23 +54,11 @@
{ -1, 0 }
};
-struct resource_spec mv_xor_res[] = {
- { SYS_RES_MEMORY, 0, RF_ACTIVE },
- { SYS_RES_IRQ, 0, RF_ACTIVE },
- { SYS_RES_IRQ, 1, RF_ACTIVE },
- { SYS_RES_IRQ, 2, RF_ACTIVE },
- { SYS_RES_IRQ, 3, RF_ACTIVE },
- { SYS_RES_IRQ, 4, RF_ACTIVE },
- { SYS_RES_IRQ, 5, RF_ACTIVE },
- { -1, 0 }
-};
-
const struct decode_win xor_win_tbl[] = {
- /* PCIE MEM */
- { 4, 0xE8, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
+ { 0 },
};
const struct decode_win *xor_wins = xor_win_tbl;
-int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win);
+int xor_wins_no = 0;
uint32_t
get_tclk(void)
==== //depot/projects/fdt/sys/arm/mv/mv_pci.c#3 (text+ko) ====
@@ -545,7 +545,7 @@
return (NULL);
rman_set_rid(res, *rid);
- rman_set_bustag(res, obio_tag);
+ rman_set_bustag(res, fdtbus_bs_tag);
rman_set_bushandle(res, start);
if (flags & RF_ACTIVE)
==== //depot/projects/fdt/sys/arm/mv/mvvar.h#8 (text+ko) ====
@@ -48,7 +48,6 @@
#define MV_TYPE_PCI 0
#define MV_TYPE_PCIE 1
-#define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */
struct gpio_config {
int gc_gpio; /* GPIO number */
@@ -66,7 +65,6 @@
extern const struct pmap_devmap pmap_devmap[];
extern const struct gpio_config mv_gpio_config[];
-extern bus_space_tag_t obio_tag;
extern const struct decode_win *idma_wins;
extern const struct decode_win *xor_wins;
extern int idma_wins_no;
==== //depot/projects/fdt/sys/arm/mv/orion/orion.c#5 (text+ko) ====
@@ -43,7 +43,6 @@
#include <arm/mv/mvvar.h>
#include <arm/mv/mvwin.h>
-
#if 0
extern const struct obio_pci_irq_map pci_irq_map[];
const struct obio_pci mv_pci_info[] = {
@@ -74,37 +73,11 @@
{ -1, 0 }
};
-/* TODO convert this to DT-derived approach. */
-/*
- * Note: the decode windows table for IDMA does not explicitly have DRAM
- * entries, which are not statically defined: active DDR banks (== windows)
- * are established in run time from actual DDR windows settings. All active
- * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
- * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
- * DDR banks are active, the remaining available IDMA decode windows for other
- * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
- */
const struct decode_win idma_win_tbl[] = {
- /* PCIE MEM */
- { 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
-
- /* PCI MEM */
- { 3, 0x59, MV_PCI_MEM_PHYS_BASE, MV_PCI_MEM_SIZE, -1 },
-
- /* Device bus BOOT */
- { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
-
- /* Device bus CS0 */
- { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
-
- /* Device bus CS1 */
- { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
-
- /* Device bus CS2 */
- { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
+ { 0 },
};
const struct decode_win *idma_wins = idma_win_tbl;
-int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
+int idma_wins_no = 0;
uint32_t
get_tclk(void)
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