PERFORCE change 162915 for review
Yohanes Nugroho
yohanes at FreeBSD.org
Thu May 28 00:26:59 UTC 2009
http://perforce.freebsd.org/chv.cgi?CH=162915
Change 162915 by yohanes at econa on 2009/05/28 00:26:38
Adding files for str91xx
Affected files ...
.. //depot/projects/str91xx/src/sys/arm/arm/cpufunc.c#2 edit
.. //depot/projects/str91xx/src/sys/arm/arm/cpufunc_asm_fa526.S#1 add
.. //depot/projects/str91xx/src/sys/arm/arm/elf_trampoline.c#2 edit
.. //depot/projects/str91xx/src/sys/arm/conf/CNS11XXNAS#1 add
.. //depot/projects/str91xx/src/sys/arm/conf/CNS11XXNAS.hints#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/econa.c#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/econa_machdep.c#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/econa_reg.h#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/econa_var.h#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/files.econa#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/if_ece.c#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/if_ece.h#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/std.econa#1 add
.. //depot/projects/str91xx/src/sys/arm/econa/timer.c#1 add
.. //depot/projects/str91xx/src/sys/arm/include/armreg.h#2 edit
.. //depot/projects/str91xx/src/sys/arm/include/cpuconf.h#2 edit
.. //depot/projects/str91xx/src/sys/arm/include/cpufunc.h#2 edit
.. //depot/projects/str91xx/src/sys/conf/Makefile.arm#2 edit
.. //depot/projects/str91xx/src/sys/conf/options.arm#2 edit
.. //depot/projects/str91xx/src/sys/dev/uart/uart_bus_ec.c#1 add
.. //depot/projects/str91xx/src/sys/dev/uart/uart_cpu_ec.c#1 add
.. //depot/projects/str91xx/src/sys/dev/usb/controller/ehci_ebus.c#1 add
.. //depot/projects/str91xx/src/sys/dev/usb/controller/ohci_ec.c#1 add
.. //depot/projects/str91xx/src/sys/dev/usb/usb_busdma.c#2 edit
.. //depot/projects/str91xx/src/sys/kern/vfs_mount.c#2 edit
Differences ...
==== //depot/projects/str91xx/src/sys/arm/arm/cpufunc.c#2 (text+ko) ====
@@ -45,7 +45,7 @@
* Created : 30/01/97
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.26 2009/05/05 12:57:16 stas Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.25 2009/01/09 10:45:04 raj Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -790,6 +790,73 @@
xscale_setup /* cpu setup */
};
#endif /* CPU_XSCALE_81342 */
+
+
+#if defined(CPU_FA526)
+struct cpu_functions fa526_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = fa526_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = armv4_tlb_flushID,
+ .cf_tlb_flushID_SE = fa526_tlb_flushID_SE,
+ .cf_tlb_flushI = armv4_tlb_flushI,
+ .cf_tlb_flushI_SE = fa526_tlb_flushI_SE,
+ .cf_tlb_flushD = armv4_tlb_flushD,
+ .cf_tlb_flushD_SE = armv4_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = fa526_icache_sync_all,
+ .cf_icache_sync_range = fa526_icache_sync_range,
+
+ .cf_dcache_wbinv_all = fa526_dcache_wbinv_all,
+ .cf_dcache_wbinv_range = fa526_dcache_wbinv_range,
+ .cf_dcache_inv_range = fa526_dcache_inv_range,
+ .cf_dcache_wb_range = fa526_dcache_wb_range,
+
+ .cf_idcache_wbinv_all = fa526_idcache_wbinv_all,
+ .cf_idcache_wbinv_range = fa526_idcache_wbinv_range,
+
+
+ .cf_l2cache_wbinv_all = cpufunc_nullop,
+ .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_inv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_wb_range = (void *)cpufunc_nullop,
+
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = fa526_flush_prefetchbuf,
+ .cf_drain_writebuf = armv4_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = fa526_flush_brnchtgt_E,
+
+ .cf_sleep = fa526_cpu_sleep,
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = fa526_context_switch,
+
+ .cf_setup = fa526_setup
+};
+#endif /* CPU_FA526 */
+
+
/*
* Global constants also used by locore.s
*/
@@ -802,6 +869,7 @@
defined (CPU_ARM9E) || defined (CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_FA526) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
static void get_cachetype_cp15(void);
@@ -1082,6 +1150,19 @@
goto out;
}
#endif /* CPU_SA1110 */
+#ifdef CPU_FA526
+ if (cputype == CPU_ID_FA526) {
+ cpufuncs = fa526_cpufuncs;
+ cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
+ get_cachetype_cp15();
+ pmap_pte_init_generic();
+
+ /* Use powersave on this CPU. */
+ cpu_do_powersave = 1;
+
+ return 0;
+ }
+#endif /* CPU_FA526 */
#ifdef CPU_IXP12X0
if (cputype == CPU_ID_IXP1200) {
cpufuncs = ixp12x0_cpufuncs;
@@ -1192,7 +1273,6 @@
#ifdef CPU_XSCALE_PXA2X0
/* ignore core revision to test PXA2xx CPUs */
if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
- (cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X ||
(cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA210) {
cpufuncs = xscale_cpufuncs;
@@ -1231,7 +1311,7 @@
*/
panic("No support for this CPU type (%08x) in kernel", cputype);
return(ARCHITECTURE_NOT_PRESENT);
-out:
+
uma_set_align(arm_dcache_align_mask);
return (0);
}
@@ -1600,7 +1680,8 @@
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
- defined(CPU_ARM10) || defined(CPU_ARM11)
+ defined(CPU_ARM10) || defined(CPU_ARM11) || \
+ defined(CPU_FA526)
#define IGN 0
#define OR 1
@@ -2066,6 +2147,60 @@
}
#endif /* CPU_SA1100 || CPU_SA1110 */
+#if defined(CPU_FA526)
+struct cpu_option fa526_options[] = {
+#ifdef COMPAT_12
+ { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
+#endif /* COMPAT_12 */
+ { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
+ { NULL, IGN, IGN, 0 }
+};
+
+void
+fa526_setup(char *args)
+{
+ int cpuctrl, cpuctrlmask;
+
+ cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
+ cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
+ | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
+ | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+ cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+ cpuctrl = parse_cpu_options(args, fa526_options, cpuctrl);
+
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+ if (vector_page == ARM_VECTORS_HIGH)
+ cpuctrl |= CPU_CONTROL_VECRELOC;
+
+ /* Clear out the cache */
+ cpu_idcache_wbinv_all();
+
+ /* Set the control register */
+ //curcpu()->ci_ctrl = cpuctrl;
+ ctrl = cpuctrl;
+ cpu_control(0xffffffff, cpuctrl);
+}
+#endif /* CPU_FA526 */
+
+
#if defined(CPU_IXP12X0)
struct cpu_option ixp12x0_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
==== //depot/projects/str91xx/src/sys/arm/arm/elf_trampoline.c#2 (text+ko) ====
@@ -57,6 +57,8 @@
#define cpu_idcache_wbinv_all arm8_cache_purgeID
#elif defined(CPU_ARM9)
#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
+#elif defined(CPU_FA526)
+#define cpu_idcache_wbinv_all fa526_idcache_wbinv_all
#elif defined(CPU_ARM9E)
#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
#elif defined(CPU_ARM10)
==== //depot/projects/str91xx/src/sys/arm/include/armreg.h#2 (text+ko) ====
@@ -178,6 +178,8 @@
#define CPU_ID_IXP435 0x69054040
#define CPU_ID_IXP465 0x69054200
+#define CPU_ID_CNS11XX 0x66015261
+
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1
#define ARM3_CP15_CONTROL 2
==== //depot/projects/str91xx/src/sys/arm/include/cpuconf.h#2 (text+ko) ====
@@ -61,6 +61,7 @@
defined(CPU_XSCALE_80200) + \
defined(CPU_XSCALE_80321) + \
defined(CPU_XSCALE_PXA2X0) + \
+ defined(CPU_FA526) + \
defined(CPU_XSCALE_IXP425))
/*
@@ -68,7 +69,7 @@
*/
#if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
- defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
+ defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425) || defined(CPU_FA526))
#define ARM_ARCH_4 1
#else
#define ARM_ARCH_4 0
@@ -125,7 +126,7 @@
#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
- defined(CPU_ARM10) || defined(CPU_ARM11))
+ defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_FA526))
#define ARM_MMU_GENERIC 1
#else
#define ARM_MMU_GENERIC 0
==== //depot/projects/str91xx/src/sys/arm/include/cpufunc.h#2 (text+ko) ====
@@ -283,6 +283,28 @@
u_int arm8_clock_config (u_int, u_int);
#endif
+
+#ifdef CPU_FA526
+void fa526_setup (char *arg);
+void fa526_setttb (u_int ttb);
+void fa526_context_switch (void);
+void fa526_cpu_sleep (int);
+void fa526_tlb_flushI_SE (u_int);
+void fa526_tlb_flushID_SE (u_int);
+void fa526_flush_prefetchbuf (void);
+void fa526_flush_brnchtgt_E (u_int);
+
+void fa526_icache_sync_all (void);
+void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
+void fa526_dcache_wbinv_all (void);
+void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
+void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
+void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
+void fa526_idcache_wbinv_all(void);
+void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
+#endif
+
+
#ifdef CPU_SA110
void sa110_setup (char *string);
void sa110_context_switch (void);
@@ -445,6 +467,7 @@
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_FA526) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
==== //depot/projects/str91xx/src/sys/conf/Makefile.arm#2 (text+ko) ====
@@ -73,7 +73,7 @@
$S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \
$S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \
$S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \
- $S/$M/$M/cpufunc_asm_sheeva.S
+ $S/$M/$M/cpufunc_asm_sheeva.S $S/$M/$M/cpufunc_asm_fa526.S
KERNEL_EXTRA=trampoline
KERNEL_EXTRA_INSTALL=kernel.gz.tramp
trampoline: ${KERNEL_KO}.tramp
==== //depot/projects/str91xx/src/sys/conf/options.arm#2 (text+ko) ====
@@ -35,3 +35,5 @@
AT91_BWCT opt_at91.h
AT91_TSC opt_at91.h
AT91_KWIKBYTE opt_at91.h
+CPU_FA526 opt_global.h
+
==== //depot/projects/str91xx/src/sys/dev/usb/usb_busdma.c#2 (text+ko) ====
@@ -660,6 +660,7 @@
}
bus_dmamap_sync(pc->tag, pc->map,
BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
+ cpu_dcache_wbinv_all();
}
/*------------------------------------------------------------------------*
@@ -674,6 +675,7 @@
}
bus_dmamap_sync(pc->tag, pc->map,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
+ cpu_dcache_wbinv_all();
}
/*------------------------------------------------------------------------*
==== //depot/projects/str91xx/src/sys/kern/vfs_mount.c#2 (text+ko) ====
@@ -1393,6 +1393,8 @@
struct timeval lastfail;
int curfail = 0;
+ pause("WAIT", hz * 10);
+
for (;;) {
DROP_GIANT();
g_waitidle();
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