PERFORCE change 162005 for review

[Arnar Mar Sig]

http://perforce.freebsd.org/chv.cgi?CH=162005

Change 162005 by antab at antab_farm on 2009/05/13 04:26:09

	* Define CACHE_LINE_SHIFT and CACHE_LINE_SIZE
	* Remove opt_kdb.h include

Affected files ...

.. //depot/projects/avr32/src/libexec/rtld-elf/avr32/rtld_machdep.h#2 edit
.. //depot/projects/avr32/src/sys/avr32/include/asm.h#6 edit
.. //depot/projects/avr32/src/sys/avr32/include/param.h#4 edit

Differences ...

==== //depot/projects/avr32/src/libexec/rtld-elf/avr32/rtld_machdep.h#2 (text+ko) ====

@@ -32,8 +32,6 @@
 #include <sys/types.h>
 #include <machine/atomic.h>
 
-#define CACHE_LINE_SIZE	  32
-
 struct Struct_Obj_Entry;
 
 /* Return the address of the .dynamic section in the dynamic linker. */

==== //depot/projects/avr32/src/sys/avr32/include/asm.h#6 (text+ko) ====

@@ -37,7 +37,6 @@
 #ifndef _MACHINE_ASM_H_
 #define	_MACHINE_ASM_H_
 
-#include "opt_kdb.h"
 #include <sys/cdefs.h>
 
 #define GLOBAL(sym)	.globl sym;		\

==== //depot/projects/avr32/src/sys/avr32/include/param.h#4 (text+ko) ====

@@ -72,6 +72,13 @@
 #define	ALIGNBYTES	_ALIGNBYTES
 #define	ALIGN(p)	_ALIGN(p)
 
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture.  It should be used with appropriate caution.
+ */
+#define CACHE_LINE_SHIFT        5
+#define CACHE_LINE_SIZE         (1 << CACHE_LINE_SHIFT)
+
 #define	PAGE_SHIFT	12
 #define	PAGE_SIZE	(1 << PAGE_SHIFT)	/* Page size */
 #define	PAGE_MASK	(PAGE_SIZE - 1)