PERFORCE change 163366 for review

[Arnar Mar Sig]

http://perforce.freebsd.org/chv.cgi?CH=163366

Change 163366 by antab at antab_farm on 2009/06/02 19:11:29

	* Set ETH_TX_DESC_WRAP for last tx buffer, forgot to wrap tx_clean_ptr
	* Fix atomic ops, atomic_cmpset should return 1 and not the value at *address, atomic_add/fetchadd are sometimes called with -1, so we must handle this.

Affected files ...

.. //depot/projects/avr32/src/sys/avr32/include/atomic.h#8 edit
.. //depot/projects/avr32/src/sys/dev/ate/if_ate.c#3 edit

Differences ...

==== //depot/projects/avr32/src/sys/avr32/include/atomic.h#8 (text+ko) ====

@@ -90,6 +90,7 @@
 		"brne	2f\n"
 		"stcond	%1, %4\n"
 		"brne	1b\n"
+		"mov	%0, 1\n"
 		"rjmp	3f\n"
 		"2:\n"
 		"mov	%0, 0\n"
@@ -110,11 +111,11 @@
 		"1:"
 		"ssrf	5\n"
 		"ld.w	%0, %2\n"
-		"add	%0, %3\n"
+		"sub	%0, %3\n"
 		"stcond	%1, %0\n"
 		"brne	1b"
 		: "=&r"(tmp), "=m"(*address)
-		: "m"(*address), "r"(val)
+		: "m"(*address), "r"(-val)
 		: "cc", "memory");
 }
 
@@ -147,12 +148,11 @@
 		"1:"
 		"ssrf	5\n"
 		"ld.w	%0, %3\n"
-		"mov	%2, %0\n"
-		"add	%2, %4\n"
+		"sub	%2, %0, %4\n"
 		"stcond	%1, %2\n"
 		"brne	1b\n"
 		: "=&r"(ret), "=m"(*address), "=r" (tmp)
-		: "m"(*address), "r"(val)
+		: "m"(*address), "r"(-val)
 		: "cc", "memory");
 
 	return ret;

==== //depot/projects/avr32/src/sys/dev/ate/if_ate.c#3 (text) ====

@@ -399,6 +399,9 @@
 	bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE);
 	sc->tx_descs[sc->txcur].addr = segs[0].ds_addr;
 	sc->tx_descs[sc->txcur].status = mapsize | ETH_TX_DESC_LAST;
+	if (sc->txcur == ATE_MAX_TX_BUFFERS - 1) {
+		sc->tx_descs[sc->txcur].status |= ETH_TX_DESC_WRAP;
+	}
 	bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_POSTWRITE);
 }
 #endif /* ATE_EMACB */
@@ -983,7 +986,7 @@
 			m_freem(sc->sent_mbuf[sc->tx_clean_ptr]);
 			sc->sent_mbuf[sc->tx_clean_ptr] = NULL;
 			ifp->if_opackets++;
-			sc->tx_clean_ptr++;
+			sc->tx_clean_ptr = (sc->tx_clean_ptr + 1) % ATE_MAX_TX_BUFFERS;
 		}
 #else /* ATE_EMACB */
 		/* XXX TSR register should be cleared */