PERFORCE change 163314 for review

Alexander Motin mav at FreeBSD.org
Mon Jun 1 21:07:14 UTC 2009


http://perforce.freebsd.org/chv.cgi?CH=163314

Change 163314 by mav at mav_mavbook on 2009/06/01 21:06:55

	Log all controller capabilities.

Affected files ...

.. //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.c#9 edit
.. //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.h#4 edit

Differences ...

==== //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.c#9 (text+ko) ====

@@ -121,7 +121,7 @@
 {
 	struct ahci_controller *ctlr = device_get_softc(dev);
 	device_t child;
-	int	error, unit;
+	int	error, unit, speed;
 	u_int32_t version, caps;
 
 	ctlr->dev = dev;
@@ -165,17 +165,41 @@
 	/* announce we support the HW */
 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
 	caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
+	speed = (caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
 	device_printf(dev,
-		  "AHCI Version %x%x.%x%x controller with %d ports PM %s\n",
-		  (version >> 24) & 0xff, (version >> 16) & 0xff,
-		  (version >> 8) & 0xff, version & 0xff,
-		  (caps & AHCI_CAP_NPMASK) + 1,
-		  (caps & AHCI_CAP_SPM) ?
-		  "supported" : "not supported");
-	device_printf(dev,
-		  "%d command slots\n",
-		  ((caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1);
-	device_printf(dev, "caps: %08x\n", caps);
+		    "AHCI v%x.%02x %sGbps controller with %d ports, PM %s\n",
+		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
+		    ((version >> 4) & 0xf0) + (version & 0x0f),
+		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
+		    ((speed == 3) ? "6":"?"))),
+		    (caps & AHCI_CAP_NPMASK) + 1,
+		    (caps & AHCI_CAP_SPM) ?
+		    "supported" : "not supported");
+	if (bootverbose) {
+		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
+		    (caps & AHCI_CAP_64BIT) ? " 64bit":"",
+		    (caps & AHCI_CAP_SNCQ) ? " NCQ":"",
+		    (caps & AHCI_CAP_SSNTF) ? " SNTF":"",
+		    (caps & AHCI_CAP_SMPS) ? " MPS":"",
+		    (caps & AHCI_CAP_SSS) ? " SS":"",
+		    (caps & AHCI_CAP_SALP) ? " ALP":"",
+		    (caps & AHCI_CAP_SAL) ? " AL":"",
+		    (caps & AHCI_CAP_SCLO) ? " CLO":"",
+		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
+		    ((speed == 3) ? "6":"?"))));
+		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
+		    (caps & AHCI_CAP_SAM) ? " AM":"",
+		    (caps & AHCI_CAP_SPM) ? " PM":"",
+		    (caps & AHCI_CAP_FBSS) ? " FBS":"",
+		    (caps & AHCI_CAP_PMD) ? " PMD":"",
+		    (caps & AHCI_CAP_SSC) ? " SSC":"",
+		    (caps & AHCI_CAP_PSC) ? " PSC":"",
+		    ((caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
+		    (caps & AHCI_CAP_CCCS) ? " CCC":"",
+		    (caps & AHCI_CAP_EMS) ? " EM":"",
+		    (caps & AHCI_CAP_SXS) ? " eSATA":"",
+		    (caps & AHCI_CAP_NPMASK) + 1);
+	}
 
 	/* attach all channels on this controller */
 	for (unit = 0; unit < ctlr->channels; unit++) {
@@ -1120,7 +1144,7 @@
 	int timeout;
 
 	/* issue Command List Override if supported */ 
-	if (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_CLO) {
+	if (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_SCLO) {
 		cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
 		cmd |= AHCI_P_CMD_CLO;
 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);

==== //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.h#4 (text+ko) ====

@@ -153,13 +153,26 @@
 /* SATA AHCI v1.0 register defines */
 #define AHCI_CAP                    0x00
 #define		AHCI_CAP_NPMASK	0x0000001f
+#define		AHCI_CAP_SXS	0x00000020
+#define		AHCI_CAP_EMS	0x00000040
+#define		AHCI_CAP_CCCS	0x00000080
 #define		AHCI_CAP_NCS	0x00001F00
 #define		AHCI_CAP_NCS_SHIFT	8
 #define		AHCI_CAP_PSC	0x00002000
 #define		AHCI_CAP_SSC	0x00004000
+#define		AHCI_CAP_PMD	0x00008000
+#define		AHCI_CAP_FBSS	0x00010000
 #define		AHCI_CAP_SPM	0x00020000
-#define		AHCI_CAP_CLO	0x01000000
+#define		AHCI_CAP_SAM	0x00080000
+#define		AHCI_CAP_ISS	0x00F00000
+#define		AHCI_CAP_ISS_SHIFT	20
+#define		AHCI_CAP_SCLO	0x01000000
+#define		AHCI_CAP_SAL	0x02000000
 #define		AHCI_CAP_SALP	0x04000000
+#define		AHCI_CAP_SSS	0x08000000
+#define		AHCI_CAP_SMPS	0x10000000
+#define		AHCI_CAP_SSNTF	0x20000000
+#define		AHCI_CAP_SNCQ	0x40000000
 #define		AHCI_CAP_64BIT	0x80000000
 
 #define AHCI_GHC                    0x04


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