PERFORCE change 160554 for review

[Andrew Turner]

http://perforce.freebsd.org/chv.cgi?CH=160554

Change 160554 by andrew at andrew_bender on 2009/04/13 08:06:17

	Rename the NAND flash registers to be device specific
	Add a subset of the S3C2440 registers

Affected files ...

.. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#8 edit
.. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2440reg.h#2 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#8 (text+ko) ====

@@ -62,17 +62,17 @@
 /* NAND Flash controller */
 #define	S3C2410_NANDFC_SIZE	0x18
 /* NANDFC_NFCONF */
-#define	 NFCONF_ENABLE	(1<<15)	/* NAND controller enabled */
-#define	 NFCONF_ECC	(1<<12)	/* Initialize ECC decoder/encoder */
-#define	 NFCONF_FCE	(1<<11)	/* Flash chip enabled */
-#define	 NFCONF_TACLS	(7<<8)	/* CLE and ALE duration */
-#define	 NFCONF_TWRPH0	(7<<4)	/* TWRPH0 duration */
-#define	 NFCONF_TWRPH1	(7<<0)	/* TWRPH1 duration */
-#define	NANDFC_NFCMD 	0x04	/* command */
-#define	NANDFC_NFADDR 	0x08	/* address */
-#define	NANDFC_NFDATA 	0x0c	/* data */
-#define	NANDFC_NFSTAT 	0x10	/* operation status */
-#define	NANDFC_NFECC	0x14	/* ecc */
+#define	 S3C2410_NFCONF_ENABLE	(1<<15)	/* NAND controller enabled */
+#define	 S3C2410_NFCONF_ECC	(1<<12)	/* Initialize ECC decoder/encoder */
+#define	 S3C2410_NFCONF_FCE	(1<<11)	/* Flash chip enabled */
+#define	 S3C2410_NFCONF_TACLS	(7<<8)	/* CLE and ALE duration */
+#define	 S3C2410_NFCONF_TWRPH0	(7<<4)	/* TWRPH0 duration */
+#define	 S3C2410_NFCONF_TWRPH1	(7<<0)	/* TWRPH1 duration */
+#define	S3C2410_NANDFC_NFCMD 	0x04	/* command */
+#define	S3C2410_NANDFC_NFADDR 	0x08	/* address */
+#define	S3C2410_NANDFC_NFDATA 	0x0c	/* data */
+#define	S3C2410_NANDFC_NFSTAT 	0x10	/* operation status */
+#define	S3C2410_NANDFC_NFECC	0x14	/* ecc */
 
 /* GPIO */
 #define	S3C2410_GPIO_SIZE	0xb4

==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2440reg.h#2 (text+ko) ====

@@ -57,6 +57,25 @@
 #define  S3C2440_CAMDIVN_HCLK4_HALF	(1<<9)
 #define  S3C2440_CAMDIVN_HCLK3_HALF	(1<<8)
 
+/* NAND Flash controller */
+#define S3C2440_NANDFC_SIZE	0x40
+
+#define S3C2440_NANDFC_NFCONT	0x04
+#define  S3C2440_NFCONT_LOCK_TIGHT	(1<<13) /* Lock part of the NAND */
+#define  S3C2440_NFCONT_SOFT_LOCK	(1<<12) /* Soft lock part of the NAND */
+#define  S3C2440_NFCONT_ILLEGAL_ACC_INT	(1<<10) /* Illegal access interrupt */
+#define  S3C2440_NFCONT_RNB_INT		(1<<9) /* RnB transition interrupt */
+#define  S3C2440_NFCONT_RNB_TRANS_MODE	(1<<8) /* RnB transition mode */
+#define  S3C2440_NFCONT_SPARE_ECC_LOCK	(1<<6) /* Lock spare ECC generation */
+#define  S3C2440_NFCONT_MAIN_ECC_LOCK	(1<<5) /* Lock main ECC generation */
+#define  S3C2440_NFCONT_INIT_ECC	(1<<4) /* Init ECC encoder/decoder */
+#define  S3C2440_NFCONT_NCE		(1<<1) /* NAND Chip select */
+#define  S3C2440_NFCONT_ENABLE		(1<<0) /* Enable the controller */
+#define S3C2440_NANDFC_NFCMMD	0x08
+#define S3C2440_NANDFC_NFADDR	0x0c
+#define S3C2440_NANDFC_NFDATA	0x10
+#define S3C2440_NANDFC_NFSTAT	0x20
+
 /* GPIO */
 #define	S3C2440_GPIO_SIZE	0xd0