PERFORCE change 153776 for review
Sam Leffler
sam at FreeBSD.org
Sat Nov 29 10:32:03 PST 2008
http://perforce.freebsd.org/chv.cgi?CH=153776
Change 153776 by sam at sam_ebb on 2008/11/29 18:31:52
add Cambria support
Affected files ...
.. //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#9 edit
Differences ...
==== //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#9 (text+ko) ====
@@ -147,105 +147,90 @@
/* Static device mappings. */
static const struct pmap_devmap ixp425_devmap[] = {
/* Physical/Virtual address for I/O space */
- {
- IXP425_IO_VBASE,
- IXP425_IO_HWBASE,
- IXP425_IO_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* Expansion Bus */
- {
- IXP425_EXP_VBASE,
- IXP425_EXP_HWBASE,
- IXP425_EXP_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* IXP425 PCI Configuration */
- {
- IXP425_PCI_VBASE,
- IXP425_PCI_HWBASE,
- IXP425_PCI_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* SDRAM Controller */
- {
- IXP425_MCU_VBASE,
- IXP425_MCU_HWBASE,
- IXP425_MCU_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* PCI Memory Space */
- {
- IXP425_PCI_MEM_VBASE,
- IXP425_PCI_MEM_HWBASE,
- IXP425_PCI_MEM_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* Q-Mgr Memory Space */
+ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
/* NPE-A Memory Space */
- {
- IXP425_NPE_A_VBASE,
- IXP425_NPE_A_HWBASE,
- IXP425_NPE_A_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* NPE-B Memory Space */
- {
- IXP425_NPE_B_VBASE,
- IXP425_NPE_B_HWBASE,
- IXP425_NPE_B_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_B_VBASE, IXP425_NPE_B_HWBASE, IXP425_NPE_B_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* NPE-C Memory Space */
- {
- IXP425_NPE_C_VBASE,
- IXP425_NPE_C_HWBASE,
- IXP425_NPE_C_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
/* MAC-A Memory Space */
- {
- IXP425_MAC_A_VBASE,
- IXP425_MAC_A_HWBASE,
- IXP425_MAC_A_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_MAC_A_VBASE, IXP425_MAC_A_HWBASE, IXP425_MAC_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* MAC-B Memory Space */
- {
- IXP425_MAC_B_VBASE,
- IXP425_MAC_B_HWBASE,
- IXP425_MAC_B_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_MAC_B_VBASE, IXP425_MAC_B_HWBASE, IXP425_MAC_B_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ { 0 },
+};
+
+/* Static device mappings. */
+static const struct pmap_devmap ixp435_devmap[] = {
+ /* Physical/Virtual address for I/O space */
+ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* Expansion Bus */
+ { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* IXP425 PCI Configuration */
+ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* DDRII Controller NB: mapped same place as IXP425 */
+ { IXP435_MCU_VBASE, IXP435_MCU_HWBASE, IXP435_MCU_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* PCI Memory Space */
+ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
/* Q-Mgr Memory Space */
- {
- IXP425_QMGR_VBASE,
- IXP425_QMGR_HWBASE,
- IXP425_QMGR_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* NPE-A Memory Space */
+ { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* NPE-C Memory Space */
+ { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* MAC-C Memory Space */
+ { IXP435_MAC_C_VBASE, IXP435_MAC_C_HWBASE, IXP435_MAC_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* MAC-A Memory Space */
+ { IXP435_MAC_A_VBASE, IXP435_MAC_A_HWBASE, IXP435_MAC_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
- {
- 0,
- 0,
- 0,
- 0,
- 0,
- }
+ { 0 }
};
extern vm_offset_t xscale_cache_clean_addr;
@@ -265,7 +250,7 @@
vm_offset_t lastaddr;
uint32_t memsize;
- set_cpufuncs();
+ set_cpufuncs(); /* NB: sets cputype */
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@@ -400,7 +385,10 @@
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
+ if (cpu_is_ixp43x())
+ pmap_devmap_bootstrap(l1pagetable, ixp435_devmap);
+ else
+ pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
@@ -436,12 +424,16 @@
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
+ /* ready to setup the console (XXX move earlier if possible) */
+ cninit();
/*
- * Fetch the SDRAM start/size from the ixp425 SDRAM configration
- * registers.
+ * Fetch the RAM size from the MCU registers. The
+ * expansion bus was mapped above so we can now read 'em.
*/
- cninit();
- memsize = ixp425_sdram_size();
+ if (cpu_is_ixp43x())
+ memsize = ixp435_ddram_size();
+ else
+ memsize = ixp425_sdram_size();
physmem = memsize / PAGE_SIZE;
/* Set stack for exception handlers */
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