PERFORCE change 136989 for review
Randall R. Stewart
rrs at FreeBSD.org
Thu Mar 6 12:48:43 UTC 2008
http://perforce.freebsd.org/chv.cgi?CH=136989
Change 136989 by rrs at rrs-mips2-jnpr on 2008/03/06 12:48:23
move ddb show oct_state to proper place.
Affected files ...
.. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#20 edit
Differences ...
==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#20 (text+ko) ====
@@ -1364,3 +1364,110 @@
platform_counter_freq = (uint64_t) (octeon_get_clock_rate());
mips_timer_init_params(platform_counter_freq, 0);
}
+
+
+#ifdef DDB
+
+#define OCTEON_POW_WQ_INT_THR 0x8001670000000080ull
+#define OCTEON_POW_WQ_INT_CNT 0x8001670000000100ull
+#define OCTEON_POW_WQ_QOS_THR 0x8001670000000180ull
+#define OCTEON_POW_WQ_INT 0x8001670000000200ull
+#define OCTEON_POW_WQ_INT_PC 0x8001670000000208ull
+
+void db_dump_intr_state(void);
+
+void
+db_dump_intr_state(void)
+{
+ uint32_t status_bits;
+ uint64_t ciu_intr_reg_addr;
+ uint64_t regstate1, regstate2;
+ int i;
+ status_bits = mips_rd_status();
+ printf("Mips SR is currently %x\n", status_bits);
+
+
+ printf("Core Interrupt summary's IP2/IP3\n");
+ ciu_intr_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR;
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ regstate2 = oct_read64(ciu_intr_reg_addr + 0x8);
+ printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+ i, ciu_intr_reg_addr, regstate1, regstate2);
+ /* next register set please */
+ ciu_intr_reg_addr += 0x10;
+ }
+ printf("Core Interrupt enable 0 IP2/IP3\n");
+ ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ regstate2 = oct_read64(ciu_intr_reg_addr + 0x10);
+ printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+ i, ciu_intr_reg_addr, regstate1, regstate2);
+ /* next register set please */
+ ciu_intr_reg_addr += 0x10;
+ }
+ printf("Core Interrupt enable 1 IP2/IP3\n");
+ ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + 0x8;
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ regstate2 = oct_read64(ciu_intr_reg_addr + 0x10);
+ printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+ i, ciu_intr_reg_addr, regstate1, regstate2);
+ /* next register set please */
+ ciu_intr_reg_addr += 0x10;
+ }
+ ciu_intr_reg_addr = OCTEON_POW_WQ_INT_THR;
+ printf("Pow Threshold registers\n");
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ printf("%llx tc:%llx tc_thr:%llx ds_thr:%llx iq_thr:%llx\n",
+ ciu_intr_reg_addr,
+ ((regstate1 >> 28) & 0x00001) ,
+ ((regstate1 >> 24) & 0x0000f),
+ ((regstate1 >> 12) & 0x003ff),
+ (regstate1 & 0x003ff));
+ ciu_intr_reg_addr += 0x8;
+ }
+ ciu_intr_reg_addr = OCTEON_POW_WQ_INT_CNT;
+ printf("Pow int cnt registers\n");
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ printf("%llx tc_cnt:%llx ds_cnt:%llx iq_cnt:%llx\n",
+ ciu_intr_reg_addr,
+ ((regstate1 >> 24) & 0x0000f),
+ ((regstate1 >> 12) & 0x003ff),
+ (regstate1 & 0x003ff));
+ ciu_intr_reg_addr += 0x8;
+ }
+
+ ciu_intr_reg_addr = OCTEON_POW_WQ_QOS_THR;
+ printf("Pow QOS thr registers\n");
+ for(i=0; i<16; i++) {
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ printf("%llx des_cnt:%llx buf_cnt:%llx free_cnt:%llx max_thr:%llx min_thr:%llx\n",
+ ciu_intr_reg_addr,
+ ((regstate1 >> 48) & 0x00fff),
+ ((regstate1 >> 36) & 0x00fff),
+ ((regstate1 >> 24) & 0x00fff),
+ ((regstate1 >> 12) & 0x003ff),
+ (regstate1 & 0x003ff));
+ ciu_intr_reg_addr += 0x8;
+ }
+ ciu_intr_reg_addr = OCTEON_POW_WQ_INT;
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ printf("POW_WQ_INT:%llx val:%llx\n", ciu_intr_reg_addr, regstate1);
+ ciu_intr_reg_addr = OCTEON_POW_WQ_INT_PC;
+ regstate1 = oct_read64(ciu_intr_reg_addr);
+ printf("POW_WQ_INT_PC:%llx val:%llx\n", ciu_intr_reg_addr, regstate1);
+}
+
+#include <sys/kernel.h>
+#include <ddb/ddb.h>
+
+DB_SHOW_COMMAND(oct_state, ddb_dump_intr_state)
+{
+ db_dump_intr_state();
+}
+
+#endif
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