PERFORCE change 136937 for review

[Randall R. Stewart]

http://perforce.freebsd.org/chv.cgi?CH=136937

Change 136937 by rrs at rrs-mips2-jnpr on 2008/03/05 18:22:37

	More enhancements in the show oct_state

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#18 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#18 (text+ko) ====

@@ -87,9 +87,6 @@
 #define uart_getreg(bas, reg)	\
 	bus_space_read_8((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
 
-int rrs_uart_debug=0;
-int rrs_uart_show_tmit_too=0;
-
 /*
  * Clear pending interrupts. THRE is cleared by reading IIR. Data
  * that may have been received gets lost here.
@@ -661,24 +658,15 @@
 				}
 			}
 			if (lsr & LSR_RXRDY) {
-				  /* This is utterly wierd. If we get
-				   * a  IIR_RLS, we should ONT just
-				   * read a LSR_RXRDY. So we will re-read the
-				   * register and the character. If the
-				   * char is 0, then its the 0 that accompanies
-				   * the BREAK and the hardware just futzed.
-				   * If its other than that, we loose and drop
-				   * the character.
-				   */
 			          xc = uart_getreg(bas, OCT_REG_RBR);
 				  lsr = uart_getreg(bas, OCT_REG_LSR);
 				  if (xc == 0) {
 				    ipend |= SER_INT_BREAK;
-				  } else {
-				    /* TSNH, but neither should this whole block */
-				    printf("We loose a char %x\n", xc);
 				  }
+				  /* else printf("We loose a char\n"); */
+
 			}
+			
 		} else if (iir == IIR_RXRDY) {
 			ipend |= SER_INT_RXREADY;
 
@@ -703,8 +691,6 @@
 			niir = uart_getreg(bas, OCT_REG_IIR);
 			lsr = uart_getreg(bas, OCT_REG_LSR);
 			usr = uart_getreg(bas, OCT_REG_USR);
-			printf("Got IIR_BUSY:%x niir:%x lsr:%x usr:%x\n",
-			       iir2, niir, lsr, usr);
 		}
 	}
 	uart_unlock(sc->sc_hwmtx);
@@ -884,6 +870,12 @@
 
 #ifdef DDB
 
+#define	OCTEON_POW_WQ_INT_THR 0x8001670000000080ull
+#define	OCTEON_POW_WQ_INT_CNT 0x8001670000000100ull
+#define	OCTEON_POW_WQ_QOS_THR 0x8001670000000180ull
+#define	OCTEON_POW_WQ_INT     0x8001670000000200ull
+#define	OCTEON_POW_WQ_INT_PC  0x8001670000000208ull
+
 void db_dump_intr_state(void);
 
 void
@@ -927,7 +919,49 @@
 	  /* next register set please */
 	  ciu_intr_reg_addr += 0x10;
 	}
+	ciu_intr_reg_addr = OCTEON_POW_WQ_INT_THR;
+	printf("Pow Threshold registers\n");
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  printf("%llx tc:%llx tc_thr:%llx ds_thr:%llx iq_thr:%llx\n",
+		 ciu_intr_reg_addr,
+		 ((regstate1 >> 28) & 0x00001) ,
+		 ((regstate1 >> 24) & 0x0000f),
+		 ((regstate1 >> 12) & 0x003ff),
+		 (regstate1 & 0x003ff));
+	  ciu_intr_reg_addr += 0x8;		 
+	}
+	ciu_intr_reg_addr = OCTEON_POW_WQ_INT_CNT;
+	printf("Pow int cnt registers\n");
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  printf("%llx tc_cnt:%llx ds_cnt:%llx iq_cnt:%llx\n",
+		 ciu_intr_reg_addr,
+		 ((regstate1 >> 24) & 0x0000f),
+		 ((regstate1 >> 12) & 0x003ff),
+		 (regstate1 & 0x003ff));
+	  ciu_intr_reg_addr += 0x8;		 
+	}
 
+	ciu_intr_reg_addr = OCTEON_POW_WQ_QOS_THR;
+	printf("Pow QOS thr registers\n");
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  printf("%llx des_cnt:%llx buf_cnt:%llx free_cnt:%llx max_thr:%llx min_thr:%llx\n",
+		 ciu_intr_reg_addr,
+		 ((regstate1 >> 48) & 0x00fff),
+		 ((regstate1 >> 36) & 0x00fff),
+		 ((regstate1 >> 24) & 0x00fff),
+		 ((regstate1 >> 12) & 0x003ff),
+		 (regstate1 & 0x003ff));
+	  ciu_intr_reg_addr += 0x8;		 
+	}
+	ciu_intr_reg_addr = OCTEON_POW_WQ_INT;
+	regstate1 = oct_read64(ciu_intr_reg_addr);
+	printf("POW_WQ_INT:%llx val:%llx\n", ciu_intr_reg_addr, regstate1);
+	ciu_intr_reg_addr = OCTEON_POW_WQ_INT_PC;	
+	regstate1 = oct_read64(ciu_intr_reg_addr);
+	printf("POW_WQ_INT_PC:%llx val:%llx\n", ciu_intr_reg_addr, regstate1);
 }
 
 #include <sys/kernel.h>