PERFORCE change 106037 for review
Warner Losh
imp at FreeBSD.org
Tue Sep 12 16:56:49 PDT 2006
http://perforce.freebsd.org/chv.cgi?CH=106037
Change 106037 by imp at imp_lighthouse on 2006/09/12 23:56:02
Refactor for better sharing.
Affected files ...
.. //depot/projects/arm/src/sys/arm/at91/at91_qdmmc.c#4 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_qdmmcreg.h#2 edit
.. //depot/projects/arm/src/sys/boot/arm/at91/libat91/at91rm9200.h#6 edit
.. //depot/projects/arm/src/sys/boot/arm/at91/libat91/mci_device.c#12 edit
.. //depot/projects/arm/src/sys/boot/arm/at91/libat91/mci_device.h#6 edit
.. //depot/projects/arm/src/sys/dev/mmc/mmcreg.h#2 edit
Differences ...
==== //depot/projects/arm/src/sys/arm/at91/at91_qdmmc.c#4 (text+ko) ====
@@ -50,6 +50,7 @@
#include <machine/intr.h>
#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91var.h>
+#include <dev/mmc/mmcreg.h>
#include <arm/at91/at91_qdmmcreg.h>
#include <arm/at91/at91_pdcreg.h>
@@ -75,6 +76,15 @@
uint32_t sector_size;
uint64_t size;
uint32_t mode;
+ uint32_t rca; /* Relative Card Address */
+ uint32_t flags;
+#define READ_PARTIAL 0x001
+#define WRITE_PARTIAL 0x002
+#define ERASE_BLOCK_EN 0x004
+#define READ_MISALIGN 0x008
+#define WRITE_MISALIGN 0x010
+ uint32_t read_bl;
+ uint32_t write_bl;
} cards[MMC_MAX];
};
@@ -153,6 +163,7 @@
static int
at91_qdmmc_sdcard_init(device_t dev)
{
+ printf("No SD cards found\n");
return (ENXIO);
}
@@ -173,7 +184,7 @@
err = at91_qdmmc_SendCommand(dev, AT91C_MMC_SEND_OP_COND_CMD,
AT91C_MMC_HOST_VOLTAGE_RANGE);
if (err != 0) {
- err = 0;
+ err = ENXIO;
printf("No MMC cards found\n");
goto out;
}
@@ -225,7 +236,7 @@
printf("MMC %i: Manufacturing Date = %i/%i\n", card, year,
month);
- sc->cards[card].addr = card + AT91C_FIRST_RCA;
+ sc->cards[card].addr = card + MMC_FIRST_RCA;
status = at91_qdmmc_SendCommand(dev,
AT91C_MMC_SET_RELATIVE_ADDR_CMD,
(sc->cards[card].addr) << 16);
@@ -269,9 +280,17 @@
sc->cards[card].size);
/* declare clockrate to 5MHz - XXX the card may allow more */
sc->cards[card].mode = 5 * MCI_MR_CLKDIV | MCI_MR_PWSDIV |
- (MCI_MR_PWSDIV << 1 | AT91C_MCI_MR_PDCMODE);
+ (MCI_MR_PWSDIV << 1 | MCI_MR_PDCMODE);
sc->cards[card].mode = 75 * MCI_MR_CLKDIV | MCI_MR_PWSDIV |
(MCI_MR_PWSDIV << 1);
+ sc->cards[card].flags = 0;
+ if (sc->cards[card].CSD[1] & CSD_1_RD_B_PAR_M)
+ sc->cards[card].flags |= READ_PARTIAL;
+ if (sc->cards[card].CSD[3] & CSD_3_WBLOCK_P_M)
+ sc->cards[card].flags |= WRITE_PARTIAL;
+ sc->cards[card].read_bl = 0;
+ sc->cards[card].write_bl = 0;
+ sc->cards[card].rca = 0;
bioq_init(&sc->cards[0].bio_queue);
}
@@ -315,10 +334,10 @@
// disable all interrupt sources
WR4(sc, MCI_IDR, 0xffffffff);
// set timeout values
- WR4(sc, MCI_DTOR, AT91C_MCI_DTOR_1MEGA_CYCLES);
+ WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1048576);
//WR4(sc, MCI_MR, AT91C_MCI_MR_PDCMODE);
// set clockrate to just 400kHz needed to identify
- WR4(sc, MCI_MR, 74 * MCI_MR_CLKDIV | MCI_MR_PWSDIV | (MCI_MR_PWSDIV << 1 | AT91C_MCI_MR_PDCMODE));
+ WR4(sc, MCI_MR, 74 * MCI_MR_CLKDIV | MCI_MR_PWSDIV | (MCI_MR_PWSDIV << 1 | MCI_MR_PDCMODE));
WR4(sc, MCI_SDCR, 0);
// enable controller
WR4(sc, MCI_CR, MCI_CR_MCIEN | MCI_CR_PWSEN);
@@ -350,9 +369,7 @@
}
if (at91_qdmmc_mmc_init(dev) != 0) {
- printf("No MMC Cards found, trying SD\n");
if (at91_qdmmc_sdcard_init(dev) != 0) {
- printf("No SD Cards found\n");
err = 0;
goto out;
}
@@ -380,7 +397,7 @@
}
/* set clockrate to 5MHz - XXX the card may allow more */
- WR4(sc, MCI_MR, 5 * MCI_MR_CLKDIV | MCI_MR_PWSDIV | (MCI_MR_PWSDIV << 1) | AT91C_MCI_MR_PDCMODE);
+ WR4(sc, MCI_MR, 5 * MCI_MR_CLKDIV | MCI_MR_PWSDIV | (MCI_MR_PWSDIV << 1) | MCI_MR_PDCMODE);
AT91_QDMMC_UNLOCK(sc);
==== //depot/projects/arm/src/sys/arm/at91/at91_qdmmcreg.h#2 (text+ko) ====
@@ -128,147 +128,4 @@
#define AT91C_NO_ARGUMENT 0x0
-/////////////////////////////////////////////////////////////////
-// Class 0 & 1 commands: Basic commands and Read Stream commands
-/////////////////////////////////////////////////////////////////
-
-#define AT91C_GO_IDLE_STATE_CMD (0 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD)
-#define AT91C_MMC_GO_IDLE_STATE_CMD (0 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_OPDCMD)
-#define AT91C_MMC_SEND_OP_COND_CMD (1 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_OPDCMD)
-#define AT91C_ALL_SEND_CID_CMD (2 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_136)
-#define AT91C_MMC_ALL_SEND_CID_CMD (2 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_136 | MCI_CMDR_OPDCMD)
-#define AT91C_SET_RELATIVE_ADDR_CMD (3 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT | MCI_CMDR_OPDCMD)
-
-#define AT91C_SET_DSR_CMD (4 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | AT91C_MCI_RSPTYP_NO | MCI_CMDR_MAXLAT) // no tested
-
-#define AT91C_SEL_DESEL_CARD_CMD (7 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_SEND_CSD_CMD (9 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_136 | MCI_CMDR_MAXLAT)
-#define AT91C_SEND_CID_CMD (10 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_136 | MCI_CMDR_MAXLAT)
-#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRDIR | MCI_CMDR_TRCMD_START | MCI_CMDR_MAXLAT)
-
-#define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_SEND_STATUS_CMD (13 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO)
-
-//*------------------------------------------------
-//* Class 2 commands: Block oriented Read commands
-//*------------------------------------------------
-
-#define AT91C_SET_BLOCKLEN_CMD (16 | MCI_CMDR_TRCMD_NO | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_READ_SINGLE_BLOCK_CMD (17 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_START | MCI_CMDR_TRTYP_BLOCK | MCI_CMDR_TRDIR | MCI_CMDR_MAXLAT)
-#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | MCI_CMDR_TRDIR | MCI_CMDR_MAXLAT)
-
-//*--------------------------------------------
-//* Class 3 commands: Sequential write commands
-//*--------------------------------------------
-
-#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 & ~(MCI_CMDR_TRDIR) | MCI_CMDR_TRCMD_START | MCI_CMDR_MAXLAT) // MMC
-
-//*------------------------------------------------
-//* Class 4 commands: Block oriented write commands
-//*------------------------------------------------
-
-#define AT91C_WRITE_BLOCK_CMD (24 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_START | (MCI_CMDR_TRTYP_BLOCK & ~(MCI_CMDR_TRDIR))| MCI_CMDR_MAXLAT)
-#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(MCI_CMDR_TRDIR)) | MCI_CMDR_MAXLAT)
-#define AT91C_PROGRAM_CSD_CMD (27 | MCI_CMDR_RSPTYP_48)
-
-
-//*----------------------------------------
-//* Class 6 commands: Group Write protect
-//*----------------------------------------
-
-#define AT91C_SET_WRITE_PROT_CMD (28 | MCI_CMDR_RSPTYP_48)
-#define AT91C_CLR_WRITE_PROT_CMD (29 | MCI_CMDR_RSPTYP_48)
-#define AT91C_SEND_WRITE_PROT_CMD (30 | MCI_CMDR_RSPTYP_48)
-
-
-//*----------------------------------------
-//* Class 5 commands: Erase commands
-//*----------------------------------------
-
-#define AT91C_TAG_SECTOR_START_CMD (32 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_TAG_SECTOR_END_CMD (33 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | MCI_CMDR_RSPTYP_48)
-#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | MCI_CMDR_RSPTYP_48)
-#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | MCI_CMDR_RSPTYP_48)
-#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | MCI_CMDR_RSPTYP_48)
-#define AT91C_ERASE_CMD (38 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-
-//*----------------------------------------
-//* Class 7 commands: Lock commands
-//*----------------------------------------
-
-#define AT91C_LOCK_UNLOCK (42 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT) // no tested
-
-//*-----------------------------------------------
-// Class 8 commands: Application specific commands
-//*-----------------------------------------------
-
-#define AT91C_APP_CMD (55 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_GEN_CMD (56 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT) // no tested
-
-#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_SDCARD_STATUS_CMD (13 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_SDCARD_APP_OP_COND_CMD (41 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO)
-#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-#define AT91C_SDCARD_SEND_SCR_CMD (51 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO | MCI_CMDR_MAXLAT)
-
-#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\
- AT91C_SDCARD_STATUS_CMD +\
- AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
- AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
- AT91C_SDCARD_APP_OP_COND_CMD +\
- AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\
- AT91C_SDCARD_SEND_SCR_CMD)
-
-//*----------------------------------------
-//* Class 9 commands: IO Mode commands
-//*----------------------------------------
-
-#define AT91C_MMC_FAST_IO_CMD (39 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_MAXLAT)
-#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | MCI_CMDR_SPCMD | MCI_CMDR_RSPTYP_48 | MCI_CMDR_TRCMD_NO| MCI_CMDR_MAXLAT)
-
-//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer
-#define AT91C_MCI_DTOR_1MEGA_CYCLES (MCI_DTOR_DTOCYC | MCI_DTOR_DTOMUL)
-
-//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock
-#define AT91C_MCI_MR_PDCMODE (75 * MCI_MR_CLKDIV |\
- MCI_MR_PWSDIV |\
- (MCI_MR_PWSDIV<<1) |\
- MCI_MR_PDCMODE)
-
-#define AT91C_VDD_16_17 (1 << 4)
-#define AT91C_VDD_17_18 (1 << 5)
-#define AT91C_VDD_18_19 (1 << 6)
-#define AT91C_VDD_19_20 (1 << 7)
-#define AT91C_VDD_20_21 (1 << 8)
-#define AT91C_VDD_21_22 (1 << 9)
-#define AT91C_VDD_22_23 (1 << 10)
-#define AT91C_VDD_23_24 (1 << 11)
-#define AT91C_VDD_24_25 (1 << 12)
-#define AT91C_VDD_25_26 (1 << 13)
-#define AT91C_VDD_26_27 (1 << 14)
-#define AT91C_VDD_27_28 (1 << 15)
-#define AT91C_VDD_28_29 (1 << 16)
-#define AT91C_VDD_29_30 (1 << 17)
-#define AT91C_VDD_30_31 (1 << 18)
-#define AT91C_VDD_31_32 (1 << 19)
-#define AT91C_VDD_32_33 (1 << 20)
-#define AT91C_VDD_33_34 (1 << 21)
-#define AT91C_VDD_34_35 (1 << 22)
-#define AT91C_VDD_35_36 (1 << 23)
-#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
-
-#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\
- AT91C_VDD_28_29 +\
- AT91C_VDD_29_30 +\
- AT91C_VDD_30_31 +\
- AT91C_VDD_31_32 +\
- AT91C_VDD_32_33)
-
-#define AT91C_FIRST_RCA 0xCAFE
#endif /* ARM_AT91_AT91QDMMCREG_H */
==== //depot/projects/arm/src/sys/boot/arm/at91/libat91/at91rm9200.h#6 (text) ====
@@ -1156,28 +1156,6 @@
#define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector
#define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
-#define AT91C_MCI_CMDNB (0x1Fu << 0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP (0x3u << 6) // (MCI) Response Type
-#define AT91C_MCI_RSPTYP_NO (0x0u << 6) // (MCI) No response
-#define AT91C_MCI_RSPTYP_48 (0x1u << 6) // (MCI) 48-bit response
-#define AT91C_MCI_RSPTYP_136 (0x2u << 6) // (MCI) 136-bit response
-#define AT91C_MCI_SPCMD (0x7u << 8) // (MCI) Special CMD
-#define AT91C_MCI_SPCMD_NONE (0x0u << 8) // (MCI) Not a special CMD
-#define AT91C_MCI_SPCMD_INIT (0x1u << 8) // (MCI) Initialization CMD
-#define AT91C_MCI_SPCMD_SYNC (0x2u << 8) // (MCI) Synchronized CMD
-#define AT91C_MCI_SPCMD_IT_CMD (0x4u << 8) // (MCI) Interrupt command
-#define AT91C_MCI_SPCMD_IT_REP (0x5u << 8) // (MCI) Interrupt response
-#define AT91C_MCI_OPDCMD (0x1u << 11) // (MCI) Open Drain Command
-#define AT91C_MCI_MAXLAT (0x1u << 12) // (MCI) Maximum Latency for Command to respond
-#define AT91C_MCI_TRCMD (0x3u << 16) // (MCI) Transfer CMD
-#define AT91C_MCI_TRCMD_NO (0x0u << 16) // (MCI) No transfer
-#define AT91C_MCI_TRCMD_START (0x1u << 16) // (MCI) Start transfer
-#define AT91C_MCI_TRCMD_STOP (0x2u << 16) // (MCI) Stop transfer
-#define AT91C_MCI_TRDIR (0x1u << 18) // (MCI) Transfer Direction
-#define AT91C_MCI_TRTYP (0x3u << 19) // (MCI) Transfer Type
-#define AT91C_MCI_TRTYP_BLOCK (0x0u << 19) // (MCI) Block Transfer type
-#define AT91C_MCI_TRTYP_MULTIPLE (0x1u << 19) // (MCI) Multiple Block transfer type
-#define AT91C_MCI_TRTYP_STREAM (0x2u << 19) // (MCI) Stream transfer type
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
#define AT91C_MCI_CMDRDY (0x1u << 0) // (MCI) Command Ready flag
#define AT91C_MCI_RXRDY (0x1u << 1) // (MCI) RX Ready flag
==== //depot/projects/arm/src/sys/boot/arm/at91/libat91/mci_device.c#12 (text+ko) ====
==== //depot/projects/arm/src/sys/boot/arm/at91/libat91/mci_device.h#6 (text+ko) ====
@@ -46,6 +46,7 @@
#ifndef __MCI_Device_h
#define __MCI_Device_h
+#include <sys/types.h>
typedef unsigned int AT91S_MCIDeviceStatus;
@@ -76,9 +77,11 @@
/* TimeOut */
#define AT91C_TIMEOUT_CMDRDY 30
-/////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
// MMC & SDCard Structures
-/////////////////////////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
/*-----------------------------------------------*/
/* SDCard Device Descriptor Structure Definition */
@@ -116,291 +119,13 @@
{
AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor
AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array
-}AT91S_MciDevice, *AT91PS_MciDevice;
+} AT91S_MciDevice, *AT91PS_MciDevice;
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MCI_CMD Register Value
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD)
+#include <dev/mmc/mmcreg.h>
-/////////////////////////////////////////////////////////////////
-// Class 0 & 1 commands: Basic commands and Read Stream commands
-/////////////////////////////////////////////////////////////////
-
-#define AT91C_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE )
-#define AT91C_MMC_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_OPDCMD)
-#define AT91C_MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)
-#define AT91C_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 )
-#define AT91C_MMC_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD)
-#define AT91C_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD)
-
-#define AT91C_SET_DSR_CMD (4 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_NO | AT91C_MCI_MAXLAT ) // no tested
-
-#define AT91C_SEL_DESEL_CARD_CMD (7 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_SEND_CSD_CMD (9 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT )
-#define AT91C_SEND_CID_CMD (10 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT )
-#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT )
-
-#define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_SEND_STATUS_CMD (13 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO )
-
-//*------------------------------------------------
-//* Class 2 commands: Block oriented Read commands
-//*------------------------------------------------
-
-#define AT91C_SET_BLOCKLEN_CMD (16 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT )
-#define AT91C_READ_SINGLE_BLOCK_CMD (17 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT)
-#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT)
-
-//*--------------------------------------------
-//* Class 3 commands: Sequential write commands
-//*--------------------------------------------
-
-#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) // MMC
-
-//*------------------------------------------------
-//* Class 4 commands: Block oriented write commands
-//*------------------------------------------------
-
-#define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT)
-#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT)
-#define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 )
-
-
-//*----------------------------------------
-//* Class 6 commands: Group Write protect
-//*----------------------------------------
-
-#define AT91C_SET_WRITE_PROT_CMD (28 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_CLR_WRITE_PROT_CMD (29 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_SEND_WRITE_PROT_CMD (30 | AT91C_MCI_RSPTYP_48 )
-
-
-//*----------------------------------------
-//* Class 5 commands: Erase commands
-//*----------------------------------------
-
-#define AT91C_TAG_SECTOR_START_CMD (32 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_TAG_SECTOR_END_CMD (33 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_ERASE_CMD (38 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT )
-
-//*----------------------------------------
-//* Class 7 commands: Lock commands
-//*----------------------------------------
-
-#define AT91C_LOCK_UNLOCK (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested
-
-//*-----------------------------------------------
-// Class 8 commands: Application specific commands
-//*-----------------------------------------------
-
-#define AT91C_APP_CMD (55 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_GEN_CMD (56 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested
-
-#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_STATUS_CMD (13 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO )
-#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SEND_SCR_CMD (51 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-
-#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\
- AT91C_SDCARD_STATUS_CMD +\
- AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
- AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
- AT91C_SDCARD_APP_OP_COND_CMD +\
- AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\
- AT91C_SDCARD_SEND_SCR_CMD)
-
-//*----------------------------------------
-//* Class 9 commands: IO Mode commands
-//*----------------------------------------
-
-#define AT91C_MMC_FAST_IO_CMD (39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT)
-#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// Functions returnals
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_CMD_SEND_OK 0 // Command ok
-#define AT91C_CMD_SEND_ERROR -1 // Command failed
-#define AT91C_INIT_OK 2 // Init Successfull
-#define AT91C_INIT_ERROR 3 // Init Failed
-#define AT91C_READ_OK 4 // Read Successfull
-#define AT91C_READ_ERROR 5 // Read Failed
-#define AT91C_WRITE_OK 6 // Write Successfull
-#define AT91C_WRITE_ERROR 7 // Write Failed
-#define AT91C_ERASE_OK 8 // Erase Successfull
-#define AT91C_ERASE_ERROR 9 // Erase Failed
-#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull
-#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MCI_SR Errors
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE |\
- AT91C_MCI_OVRE |\
- AT91C_MCI_DTOE |\
- AT91C_MCI_DCRCE |\
- AT91C_MCI_RTOE |\
- AT91C_MCI_RENDE |\
- AT91C_MCI_RCRCE |\
- AT91C_MCI_RDIRE |\
- AT91C_MCI_RINDE)
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-// OCR Register
-////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_VDD_16_17 (1 << 4)
-#define AT91C_VDD_17_18 (1 << 5)
-#define AT91C_VDD_18_19 (1 << 6)
-#define AT91C_VDD_19_20 (1 << 7)
-#define AT91C_VDD_20_21 (1 << 8)
-#define AT91C_VDD_21_22 (1 << 9)
-#define AT91C_VDD_22_23 (1 << 10)
-#define AT91C_VDD_23_24 (1 << 11)
-#define AT91C_VDD_24_25 (1 << 12)
-#define AT91C_VDD_25_26 (1 << 13)
-#define AT91C_VDD_26_27 (1 << 14)
-#define AT91C_VDD_27_28 (1 << 15)
-#define AT91C_VDD_28_29 (1 << 16)
-#define AT91C_VDD_29_30 (1 << 17)
-#define AT91C_VDD_30_31 (1 << 18)
-#define AT91C_VDD_31_32 (1 << 19)
-#define AT91C_VDD_32_33 (1 << 20)
-#define AT91C_VDD_33_34 (1 << 21)
-#define AT91C_VDD_34_35 (1 << 22)
-#define AT91C_VDD_35_36 (1 << 23)
-#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
-
-#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\
- AT91C_VDD_28_29 +\
- AT91C_VDD_29_30 +\
- AT91C_VDD_30_31 +\
- AT91C_VDD_31_32 +\
- AT91C_VDD_32_33)
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
-////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus
-#define AT91C_SR_IDLE (0 << 9)
-#define AT91C_SR_READY (1 << 9)
-#define AT91C_SR_IDENT (2 << 9)
-#define AT91C_SR_STBY (3 << 9)
-#define AT91C_SR_TRAN (4 << 9)
-#define AT91C_SR_DATA (5 << 9)
-#define AT91C_SR_RCV (6 << 9)
-#define AT91C_SR_PRG (7 << 9)
-#define AT91C_SR_DIS (8 << 9)
-
-#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MMC CSD register header File
-// CSD_x_xxx_S for shift value for word x
-// CSD_x_xxx_M for mask value for word x
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// First Response INT <=> CSD[3] : bits 0 to 31
-#define CSD_3_BIT0_S 0 // [0:0]
-#define CSD_3_BIT0_M 0x01
-#define CSD_3_CRC_S 1 // [7:1]
-#define CSD_3_CRC_M 0x7F
-#define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility
-#define CSD_3_MMC_ECC_M 0x03
-#define CSD_3_FILE_FMT_S 10 // [11:10]
-#define CSD_3_FILE_FMT_M 0x03
-#define CSD_3_TMP_WP_S 12 // [12:12]
-#define CSD_3_TMP_WP_M 0x01
-#define CSD_3_PERM_WP_S 13 // [13:13]
-#define CSD_3_PERM_WP_M 0x01
-#define CSD_3_COPY_S 14 // [14:14]
-#define CSD_3_COPY_M 0x01
-#define CSD_3_FILE_FMT_GRP_S 15 // [15:15]
-#define CSD_3_FILE_FMT_GRP_M 0x01
-// reserved 16 // [20:16]
-// reserved 0x1F
-#define CSD_3_WBLOCK_P_S 21 // [21:21]
-#define CSD_3_WBLOCK_P_M 0x01
-#define CSD_3_WBLEN_S 22 // [25:22]
-#define CSD_3_WBLEN_M 0x0F
-#define CSD_3_R2W_F_S 26 // [28:26]
-#define CSD_3_R2W_F_M 0x07
-#define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility
-#define CSD_3_MMC_DEF_ECC_M 0x03
-#define CSD_3_WP_GRP_EN_S 31 // [31:31]
-#define CSD_3_WP_GRP_EN_M 0x01
-
-// Seconde Response INT <=> CSD[2] : bits 32 to 63
-#define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32]
-#define CSD_2_v21_WP_GRP_SIZE_M 0x7F
-#define CSD_2_v21_SECT_SIZE_S 7 // [45:39]
-#define CSD_2_v21_SECT_SIZE_M 0x7F
-#define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46]
-#define CSD_2_v21_ER_BLEN_EN_M 0x01
-
-#define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32]
-#define CSD_2_v22_WP_GRP_SIZE_M 0x1F
-#define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37]
-#define CSD_2_v22_ER_GRP_SIZE_M 0x1F
-#define CSD_2_v22_SECT_SIZE_S 10 // [46:42]
-#define CSD_2_v22_SECT_SIZE_M 0x1F
-
-#define CSD_2_C_SIZE_M_S 15 // [49:47]
-#define CSD_2_C_SIZE_M_M 0x07
-#define CSD_2_VDD_WMAX_S 18 // [52:50]
-#define CSD_2_VDD_WMAX_M 0x07
-#define CSD_2_VDD_WMIN_S 21 // [55:53]
-#define CSD_2_VDD_WMIN_M 0x07
-#define CSD_2_RCUR_MAX_S 24 // [58:56]
-#define CSD_2_RCUR_MAX_M 0x07
-#define CSD_2_RCUR_MIN_S 27 // [61:59]
-#define CSD_2_RCUR_MIN_M 0x07
-#define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE
-#define CSD_2_CSIZE_L_M 0x03
-
-// Third Response INT <=> CSD[1] : bits 64 to 95
-#define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE
-#define CSD_1_CSIZE_H_M 0x03FF
-// reserved 10 // [75:74]
-// reserved 0x03
-#define CSD_1_DSR_I_S 12 // [76:76]
-#define CSD_1_DSR_I_M 0x01
-#define CSD_1_RD_B_MIS_S 13 // [77:77]
-#define CSD_1_RD_B_MIS_M 0x01
-#define CSD_1_WR_B_MIS_S 14 // [78:78]
-#define CSD_1_WR_B_MIS_M 0x01
-#define CSD_1_RD_B_PAR_S 15 // [79:79]
-#define CSD_1_RD_B_PAR_M 0x01
-#define CSD_1_RD_B_LEN_S 16 // [83:80]
-#define CSD_1_RD_B_LEN_M 0x0F
-#define CSD_1_CCC_S 20 // [95:84]
-#define CSD_1_CCC_M 0x0FFF
-
-// Fourth Response INT <=> CSD[0] : bits 96 to 127
-#define CSD_0_TRANS_SPEED_S 0 // [103:96]
-#define CSD_0_TRANS_SPEED_M 0xFF
-#define CSD_0_NSAC_S 8 // [111:104]
-#define CSD_0_NSAC_M 0xFF
-#define CSD_0_TAAC_S 16 // [119:112]
-#define CSD_0_TAAC_M 0xFF
-// reserved 24 // [121:120]
-// reserved 0x03
-#define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility
-#define CSD_0_MMC_SPEC_VERS_M 0x0F
-#define CSD_0_STRUCT_S 30 // [127:126]
-#define CSD_0_STRUCT_M 0x03
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \
+ AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \
+ AT91C_MCI_RDIRE | AT91C_MCI_RINDE)
void AT91F_MCI_Device_Handler(AT91PS_MciDevice,unsigned int);
AT91S_MCIDeviceStatus AT91F_MCI_SDCard_Init (AT91PS_MciDevice);
==== //depot/projects/arm/src/sys/dev/mmc/mmcreg.h#2 (text+ko) ====
@@ -81,4 +81,328 @@
void *done_data; /* requestor set data */
};
-#endif /* DEV_MMC_BRIDGE_H */
+#define MMC_CMDNB (0x1Fu << 0) // Command Number
+#define MMC_RSPTYP (0x3u << 6) // Response Type
+#define MMC_RSPTYP_NO (0x0u << 6) // No response
+#define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response
+#define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response
+#define MMC_SPCMD (0x7u << 8) // Special CMD
+#define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD
+#define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD
+#define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD
+#define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command
+#define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response
+#define MMC_OPDCMD (0x1u << 11) // Open Drain Command
+#define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond
+#define MMC_TRCMD (0x3u << 16) // Transfer CMD
+#define MMC_TRCMD_NO (0x0u << 16) // No transfer
+#define MMC_TRCMD_START (0x1u << 16) // Start transfer
+#define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer
+#define MMC_TRDIR (0x1u << 18) // Transfer Direction
+#define MMC_TRTYP (0x3u << 19) // Transfer Type
+#define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type
+#define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type
+#define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type
+
+///////////////////////////////////////////////////////////////////////////////
+// MCI_CMD Register Value
+///////////////////////////////////////////////////////////////////////////////
+#define AT91C_POWER_ON_INIT \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD)
+
+/////////////////////////////////////////////////////////////////
+// Class 0 & 1 commands: Basic commands and Read Stream commands
+/////////////////////////////////////////////////////////////////
+
+#define AT91C_GO_IDLE_STATE_CMD \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE )
+#define AT91C_MMC_GO_IDLE_STATE_CMD \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD)
+#define AT91C_MMC_SEND_OP_COND_CMD \
+ (1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_OPDCMD)
+
+#define AT91C_ALL_SEND_CID_CMD \
+ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136)
+#define AT91C_MMC_ALL_SEND_CID_CMD \
+ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_OPDCMD)
+
+#define AT91C_SET_RELATIVE_ADDR_CMD \
+ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define AT91C_MMC_SET_RELATIVE_ADDR_CMD \
+ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT | MMC_OPDCMD)
+
+#define AT91C_SET_DSR_CMD \
+ (4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \
+ MMC_MAXLAT) // no tested
+
+#define AT91C_SEL_DESEL_CARD_CMD \
+ (7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define AT91C_SEND_CSD_CMD \
+ (9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_MAXLAT)
+#define AT91C_SEND_CID_CMD \
+ (10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_MAXLAT)
+#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD \
+ (11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \
+ MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \
+ MMC_MAXLAT)
+
+#define AT91C_STOP_TRANSMISSION_CMD \
+ (12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define AT91C_STOP_TRANSMISSION_SYNC_CMD \
+ (12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define AT91C_SEND_STATUS_CMD \
+ (13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define AT91C_GO_INACTIVE_STATE_CMD \
+ (15 | MMC_RSPTYP_NO)
+
+//*------------------------------------------------
+//* Class 2 commands: Block oriented Read commands
+//*------------------------------------------------
+
+#define AT91C_SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT )
+#define AT91C_READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT)
+#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT)
+
+//*--------------------------------------------
+//* Class 3 commands: Sequential write commands
+//*--------------------------------------------
+
+#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC
+
+//*------------------------------------------------
+//* Class 4 commands: Block oriented write commands
+//*------------------------------------------------
+
+#define AT91C_WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT)
+#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT)
+#define AT91C_PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 )
+
+
+//*----------------------------------------
+//* Class 6 commands: Group Write protect
+//*----------------------------------------
+
+#define AT91C_SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 )
+#define AT91C_CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 )
+#define AT91C_SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 )
+
+
+//*----------------------------------------
+//* Class 5 commands: Erase commands
+//*----------------------------------------
+
+#define AT91C_TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 )
+#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 )
+#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 )
+#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 )
+#define AT91C_ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT )
+
+//*----------------------------------------
+//* Class 7 commands: Lock commands
+//*----------------------------------------
+
+#define AT91C_LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
+
+//*-----------------------------------------------
+// Class 8 commands: Application specific commands
+//*-----------------------------------------------
+
+#define AT91C_APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
+
+#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO )
+#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define AT91C_SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+
+#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\
+ AT91C_SDCARD_STATUS_CMD +\
+ AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
+ AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
+ AT91C_SDCARD_APP_OP_COND_CMD +\
+ AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\
+ AT91C_SDCARD_SEND_SCR_CMD)
+
+//*----------------------------------------
+//* Class 9 commands: IO Mode commands
+//*----------------------------------------
+
+#define AT91C_MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT)
+#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////
+// Functions returnals
+/////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AT91C_CMD_SEND_OK 0 // Command ok
+#define AT91C_CMD_SEND_ERROR -1 // Command failed
+#define AT91C_INIT_OK 2 // Init Successfull
+#define AT91C_INIT_ERROR 3 // Init Failed
+#define AT91C_READ_OK 4 // Read Successfull
+#define AT91C_READ_ERROR 5 // Read Failed
+#define AT91C_WRITE_OK 6 // Write Successfull
+#define AT91C_WRITE_ERROR 7 // Write Failed
+#define AT91C_ERASE_OK 8 // Erase Successfull
+#define AT91C_ERASE_ERROR 9 // Erase Failed
+#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull
+#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed
+
+////////////////////////////////////////////////////////////////////////////////
+// OCR Register
+////////////////////////////////////////////////////////////////////////////////
+#define AT91C_VDD_16_17 (1 << 4)
+#define AT91C_VDD_17_18 (1 << 5)
+#define AT91C_VDD_18_19 (1 << 6)
+#define AT91C_VDD_19_20 (1 << 7)
+#define AT91C_VDD_20_21 (1 << 8)
+#define AT91C_VDD_21_22 (1 << 9)
+#define AT91C_VDD_22_23 (1 << 10)
+#define AT91C_VDD_23_24 (1 << 11)
+#define AT91C_VDD_24_25 (1 << 12)
+#define AT91C_VDD_25_26 (1 << 13)
+#define AT91C_VDD_26_27 (1 << 14)
+#define AT91C_VDD_27_28 (1 << 15)
+#define AT91C_VDD_28_29 (1 << 16)
+#define AT91C_VDD_29_30 (1 << 17)
+#define AT91C_VDD_30_31 (1 << 18)
+#define AT91C_VDD_31_32 (1 << 19)
+#define AT91C_VDD_32_33 (1 << 20)
+#define AT91C_VDD_33_34 (1 << 21)
+#define AT91C_VDD_34_35 (1 << 22)
+#define AT91C_VDD_35_36 (1 << 23)
+#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
+
+#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \
+ AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33)
+
+////////////////////////////////////////////////////////////////////////////////
+// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
+////////////////////////////////////////////////////////////////////////////////
+#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus
+#define AT91C_SR_IDLE (0 << 9)
+#define AT91C_SR_READY (1 << 9)
+#define AT91C_SR_IDENT (2 << 9)
+#define AT91C_SR_STBY (3 << 9)
+#define AT91C_SR_TRAN (4 << 9)
+#define AT91C_SR_DATA (5 << 9)
+#define AT91C_SR_RCV (6 << 9)
+#define AT91C_SR_PRG (7 << 9)
+#define AT91C_SR_DIS (8 << 9)
+
+#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
+
+#define MMC_FIRST_RCA 0xCAFE
+
+////////////////////////////////////////////////////////////////////////////////
+// MMC CSD register header File
+// CSD_x_xxx_S for shift value for word x
+// CSD_x_xxx_M for mask value for word x
+////////////////////////////////////////////////////////////////////////////////
+
+// First Response INT <=> CSD[3] : bits 0 to 31
+#define CSD_3_BIT0_S 0 // [0:0]
+#define CSD_3_BIT0_M 0x01
+#define CSD_3_CRC_S 1 // [7:1]
+#define CSD_3_CRC_M 0x7F
+#define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility
+#define CSD_3_MMC_ECC_M 0x03
+#define CSD_3_FILE_FMT_S 10 // [11:10]
+#define CSD_3_FILE_FMT_M 0x03
+#define CSD_3_TMP_WP_S 12 // [12:12]
+#define CSD_3_TMP_WP_M 0x01
+#define CSD_3_PERM_WP_S 13 // [13:13]
+#define CSD_3_PERM_WP_M 0x01
+#define CSD_3_COPY_S 14 // [14:14]
+#define CSD_3_COPY_M 0x01
+#define CSD_3_FILE_FMT_GRP_S 15 // [15:15]
+#define CSD_3_FILE_FMT_GRP_M 0x01
+// reserved 16 // [20:16]
+// reserved 0x1F
+#define CSD_3_WBLOCK_P_S 21 // [21:21]
+#define CSD_3_WBLOCK_P_M 0x01
+#define CSD_3_WBLEN_S 22 // [25:22]
+#define CSD_3_WBLEN_M 0x0F
+#define CSD_3_R2W_F_S 26 // [28:26]
+#define CSD_3_R2W_F_M 0x07
+#define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility
+#define CSD_3_MMC_DEF_ECC_M 0x03
+#define CSD_3_WP_GRP_EN_S 31 // [31:31]
+#define CSD_3_WP_GRP_EN_M 0x01
+
+// Seconde Response INT <=> CSD[2] : bits 32 to 63
+#define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32]
+#define CSD_2_v21_WP_GRP_SIZE_M 0x7F
+#define CSD_2_v21_SECT_SIZE_S 7 // [45:39]
+#define CSD_2_v21_SECT_SIZE_M 0x7F
+#define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46]
+#define CSD_2_v21_ER_BLEN_EN_M 0x01
+
+#define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32]
+#define CSD_2_v22_WP_GRP_SIZE_M 0x1F
+#define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37]
+#define CSD_2_v22_ER_GRP_SIZE_M 0x1F
+#define CSD_2_v22_SECT_SIZE_S 10 // [46:42]
+#define CSD_2_v22_SECT_SIZE_M 0x1F
+
+#define CSD_2_C_SIZE_M_S 15 // [49:47]
+#define CSD_2_C_SIZE_M_M 0x07
+#define CSD_2_VDD_WMAX_S 18 // [52:50]
+#define CSD_2_VDD_WMAX_M 0x07
+#define CSD_2_VDD_WMIN_S 21 // [55:53]
+#define CSD_2_VDD_WMIN_M 0x07
+#define CSD_2_RCUR_MAX_S 24 // [58:56]
+#define CSD_2_RCUR_MAX_M 0x07
+#define CSD_2_RCUR_MIN_S 27 // [61:59]
+#define CSD_2_RCUR_MIN_M 0x07
+#define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE
+#define CSD_2_CSIZE_L_M 0x03
+
+// Third Response INT <=> CSD[1] : bits 64 to 95
+#define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE
+#define CSD_1_CSIZE_H_M 0x03FF
+// reserved 10 // [75:74]
+// reserved 0x03
+#define CSD_1_DSR_I_S 12 // [76:76]
+#define CSD_1_DSR_I_M 0x01
+#define CSD_1_RD_B_MIS_S 13 // [77:77]
+#define CSD_1_RD_B_MIS_M 0x01
+#define CSD_1_WR_B_MIS_S 14 // [78:78]
+#define CSD_1_WR_B_MIS_M 0x01
+#define CSD_1_RD_B_PAR_S 15 // [79:79]
+#define CSD_1_RD_B_PAR_M 0x01
+#define CSD_1_RD_B_LEN_S 16 // [83:80]
+#define CSD_1_RD_B_LEN_M 0x0F
+#define CSD_1_CCC_S 20 // [95:84]
+#define CSD_1_CCC_M 0x0FFF
+
+// Fourth Response INT <=> CSD[0] : bits 96 to 127
+#define CSD_0_TRANS_SPEED_S 0 // [103:96]
+#define CSD_0_TRANS_SPEED_M 0xFF
+#define CSD_0_NSAC_S 8 // [111:104]
+#define CSD_0_NSAC_M 0xFF
+#define CSD_0_TAAC_S 16 // [119:112]
+#define CSD_0_TAAC_M 0xFF
+// reserved 24 // [121:120]
+// reserved 0x03
+#define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility
+#define CSD_0_MMC_SPEC_VERS_M 0x0F
+#define CSD_0_STRUCT_S 30 // [127:126]
+#define CSD_0_STRUCT_M 0x03
+
+////////////////////////////////////////////////////////////////////////////////
+
+#endif /* DEV_MMCREG_H */
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