PERFORCE change 107378 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=107378

Change 107378 by imp at imp_lighthouse on 2006/10/06 21:55:51

	Expand the control over the GPIO a bit.

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_pio.c#21 edit
.. //depot/projects/arm/src/sys/sys/gpio.h#5 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_pio.c#21 (text+ko) ====

@@ -274,6 +274,7 @@
 {
 	struct at91_pio_softc *sc = CDEV2SOFTC(dev);
 	struct gpio_cfg *cfg;
+	struct gpio_info *info;
 
 	switch(cmd) {
 	case GPIO_SET:	/* turn bits on */
@@ -282,30 +283,52 @@
 	case GPIO_CLR:	/* turn bits off */
 		WR4(sc, PIO_CODR, *(uint32_t *)data);
 		return (0);
-	case GPIO_GET:	/* Get the status of output bits */
-		*(uint32_t *)data = RD4(sc, PIO_ODSR);
-		return (0);
 	case GPIO_READ:	/* Get the status of input bits */
 		*(uint32_t *)data = RD4(sc, PIO_PDSR);
 		return (0);
 	case GPIO_CFG:	/* Configure GPIO pins */
 		cfg = (struct gpio_cfg *)data;
 		if (cfg->cfgmask & GPIO_CFG_INPUT) {
-			WR4(sc, PIO_PER, cfg->iomask);
 			WR4(sc, PIO_OER, cfg->iomask & ~cfg->input);
 			WR4(sc, PIO_ODR, cfg->iomask & cfg->input);
 		}
 		if (cfg->cfgmask & GPIO_CFG_HI_Z) {
-			WR4(sc, PIO_MDER, cfg->iomask & ~cfg->hi_z);
-			WR4(sc, PIO_MDDR, cfg->iomask & cfg->hi_z);
+			WR4(sc, PIO_MDDR, cfg->iomask & ~cfg->hi_z);
+			WR4(sc, PIO_MDER, cfg->iomask & cfg->hi_z);
 		}
 		if (cfg->cfgmask & GPIO_CFG_PULLUP) {
-			WR4(sc, PIO_PUER, cfg->iomask & ~cfg->pullup);
-			WR4(sc, PIO_PUDR, cfg->iomask & cfg->pullup);
+			WR4(sc, PIO_PUDR, cfg->iomask & ~cfg->pullup);
+			WR4(sc, PIO_PUER, cfg->iomask & cfg->pullup);
+		}
+		if (cfg->cfgmask & GPIO_CFG_GLITCH) {
+			WR4(sc, PIO_IFDR, cfg->iomask & ~cfg->pullup);
+			WR4(sc, PIO_IFER, cfg->iomask & cfg->pullup);
+		}
+		if (cfg->cfgmask & GPIO_CFG_ENABLED) {
+			WR4(sc, PIO_PDR, cfg->iomask & ~cfg->pullup);
+			WR4(sc, PIO_PER, cfg->iomask & cfg->pullup);
+		}
+		if (cfg->cfgmask & GPIO_CFG_PERIPH) {
+			WR4(sc, PIO_ASR, cfg->iomask & ~cfg->pullup);
+			WR4(sc, PIO_BSR, cfg->iomask & cfg->pullup);
+		}
+		if (cfg->cfgmask & GPIO_CFG_ISR) {
+			WR4(sc, PIO_IDR, cfg->iomask & ~cfg->pullup);
+			WR4(sc, PIO_IER, cfg->iomask & cfg->pullup);
 		}
 		return (0);
 	case GPIO_INFO:	/* Learn about this device's GPIO bits */
-		break;
+		info = (struct gpio_info *)data;
+		info->output_status = RD4(sc, PIO_ODSR);
+		info->input_status = RD4(sc, PIO_OSR);
+		info->highz_status = RD4(sc, PIO_MDSR);
+		info->pullup_status = RD4(sc, PIO_PUSR);
+		info->glitch_status = RD4(sc, PIO_IFSR);
+		info->enabled_status = RD4(sc, PIO_PSR);
+		info->periph_status = RD4(sc, PIO_ABSR);
+		info->intr_status = RD4(sc, PIO_ISR);
+		memset(info->extra_status, 0, sizeof(info->extra_status));
+		return (0);
 	}
 	return (ENOTTY);
 }

==== //depot/projects/arm/src/sys/sys/gpio.h#5 (text+ko) ====

@@ -35,26 +35,40 @@
 
 struct gpio_info
 {
-    int dummy;
+	uint32_t	output_status;	/* Current state of output pins */
+	uint32_t	input_status;	/* 1->in 0->out bitmask */
+	uint32_t	highz_status;	/* 1->highz 0->driven bitmask */
+	uint32_t	pullup_status;	/* 1->pullup engaged 0->floating */
+	uint32_t	glitch_status;	/* 0-> no glitch filter 1->gf */
+	uint32_t	enabled_status;	/* 1->used for gpio 0->other */
+	uint32_t	periph_status;	/* 0->A periph 1->B periph */
+	uint32_t	intr_status;	/* 1-> ISR enabled, 0->disabled */
+	uint32_t	extra_status[8];/* Extra status info, device depend */
 };
 
 struct gpio_cfg
 {
 	uint32_t	cfgmask; 	/* which things change */
-#define	GPIO_CFG_INPUT	1
-#define	GPIO_CFG_HI_Z	2
-#define	GPIO_CFG_PULLUP	4
+#define	GPIO_CFG_INPUT		1	/* configure input/output pins */
+#define	GPIO_CFG_HI_Z		2	/* HiZ */
+#define	GPIO_CFG_PULLUP		4	/* Enable/disable pullup resistors */
+#define GPIO_CFG_GLITCH		8	/* Glitch filtering */
+#define GPIO_CFG_ENABLED	0x10	/* Use pin for GPIO or other */
+#define	GPIO_CFG_PERIPH		0x20	/* Select which peripheral to use */
+#define	GPIO_CFG_ISR		0x40	/* Select pin for ISR */
 	uint32_t	iomask;		/* Mask of bits to change */
 	uint32_t	input;		/* or output */
 	uint32_t	hi_z;		/* Disable output */
 	uint32_t	pullup;		/* Enable pullup resistor */
+	uint32_t	glitch;		/* Glitch filtering */
+	uint32_t	enabled;	/* Enabled for GPIO (1) or other (0) */
+	uint32_t	periph;		/* Select which periph, if possible */
 };
 
 #define GPIO_SET	_IOW('g', 0, uint32_t)	/* Turn bits on */
 #define GPIO_CLR	_IOW('g', 1, uint32_t)	/* Turn bits off */
-#define GPIO_GET	_IOR('g', 2, uint32_t)	/* Read output bit state */
-#define GPIO_READ	_IOR('g', 3, uint32_t)	/* Read input bit state */
-#define GPIO_INFO	_IOR('g', 4, struct gpio_info)	/* State of gpio cfg */
-#define GPIO_CFG	_IOW('g', 5, struct gpio_cfg)	/* Configure gpio */
+#define GPIO_READ	_IOR('g', 2, uint32_t)	/* Read input bit state */
+#define GPIO_INFO	_IOR('g', 3, struct gpio_info)	/* State of gpio cfg */
+#define GPIO_CFG	_IOW('g', 4, struct gpio_cfg)	/* Configure gpio */
 
 #endif /* _SYS_GPIO_H */