PERFORCE change 93916 for review
Warner Losh
imp at FreeBSD.org
Fri Mar 24 06:44:04 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=93916
Change 93916 by imp at imp_Speedy on 2006/03/24 06:43:38
rtc working. but it is of dubious value since we don't need
it to keep time, and it is reset to 1-1-1998 on reboot.
Affected files ...
.. //depot/projects/arm/src/sys/arm/at91/at91_rtc.c#2 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_rtcreg.h#2 edit
Differences ...
==== //depot/projects/arm/src/sys/arm/at91/at91_rtc.c#2 (text+ko) ====
@@ -28,6 +28,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/clock.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/lock.h>
@@ -40,6 +41,8 @@
#include <arm/at91/at91_rtcreg.h>
+#include "clock_if.h"
+
struct at91_rtc_softc
{
device_t dev; /* Myself */
@@ -61,11 +64,11 @@
bus_write_4(sc->mem_res, off, val);
}
-#define AT91_RTC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
-#define AT91_RTC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+#define AT91_RTC_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
+#define AT91_RTC_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
#define AT91_RTC_LOCK_INIT(_sc) \
mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
- "rtc", MTX_DEF)
+ "rtc", MTX_SPIN)
#define AT91_RTC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
#define AT91_RTC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
#define AT91_RTC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
@@ -113,6 +116,7 @@
AT91_RTC_LOCK_DESTROY(sc);
goto out;
}
+ clock_register(dev, 1000000);
out:;
if (err)
at91_rtc_deactivate(dev);
@@ -187,12 +191,53 @@
return;
}
+/*
+ * Get the time of day clock and return it in ts.
+ * Return 0 on success, an error number otherwise.
+ */
+static int
+at91_rtc_gettime(device_t dev, struct timespec *ts)
+{
+ struct clocktime ct;
+ uint32_t timr, calr;
+ struct at91_rtc_softc *sc;
+
+ sc = device_get_softc(dev);
+ timr = RD4(sc, RTC_TIMR);
+ calr = RD4(sc, RTC_CALR);
+ ct.nsec = 0;
+ ct.sec = RTC_TIMR_SEC(timr);
+ ct.min = RTC_TIMR_MIN(timr);
+ ct.hour = RTC_TIMR_HR(timr);
+ ct.year = RTC_CALR_CEN(calr) * 100 + RTC_CALR_YEAR(calr);
+ ct.mon = RTC_CALR_MON(calr);
+ ct.day = RTC_CALR_DAY(calr);
+ ct.dow = -1;
+ return clock_ct_to_ts(&ct, ts);
+}
+
+/*
+ * Set the time of day clock based on the value of the struct timespec arg.
+ * Return 0 on success, an error number otherwise.
+ */
+static int
+at91_rtc_settime(device_t dev, struct timespec *ts)
+{
+ // XXX UGLY XXX
+ printf("SET TIME\n");
+ return (EINVAL);
+}
+
static device_method_t at91_rtc_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, at91_rtc_probe),
DEVMETHOD(device_attach, at91_rtc_attach),
DEVMETHOD(device_detach, at91_rtc_detach),
+ /* clock interface */
+ DEVMETHOD(clock_gettime, at91_rtc_gettime),
+ DEVMETHOD(clock_settime, at91_rtc_settime),
+
{ 0, 0 }
};
==== //depot/projects/arm/src/sys/arm/at91/at91_rtcreg.h#2 (text+ko) ====
@@ -28,41 +28,56 @@
#define ARM_AT91_AT91_RTCREG_H
/* Registers */
-#define RTC_PER 0x00 /* RTC Enable Register */
-#define RTC_PDR 0x04 /* RTC Disable Register */
-#define RTC_PSR 0x08 /* RTC Status Register */
- /* 0x0c reserved */
-#define RTC_OER 0x10 /* RTC Output Enable Register */
-#define RTC_ODR 0x14 /* RTC Output Disable Register */
-#define RTC_OSR 0x18 /* RTC Output Status Register */
- /* 0x1c reserved */
-#define RTC_IFER 0x20 /* RTC Glitch Input Enable Register */
-#define RTC_IFDR 0x24 /* RTC Glitch Input Disable Register */
-#define RTC_IFSR 0x28 /* RTC Glitch Input Status Register */
- /* 0x2c reserved */
-#define RTC_SODR 0x30 /* RTC Set Output Data Register */
-#define RTC_CODR 0x34 /* RTC Clear Output Data Register */
-#define RTC_ODSR 0x38 /* RTC Output Data Status Register */
-#define RTC_PDSR 0x3c /* RTC Pin Data Status Register */
-#define RTC_IER 0x40 /* RTC Interrupt Enable Register */
-#define RTC_IDR 0x44 /* RTC Interrupt Disable Register */
-#define RTC_IMR 0x48 /* RTC Interrupt Mask Register */
-#define RTC_ISR 0x4c /* RTC Interrupt Status Register */
-#define RTC_MDER 0x50 /* RTC Multi-Driver Enable Register */
-#define RTC_MDDR 0x54 /* RTC Multi-Driver Disable Register */
-#define RTC_MDSR 0x58 /* RTC Multi-Driver Status Register */
- /* 0x5c reserved */
-#define RTC_PUER 0x60 /* RTC Pull-up Enable Register */
-#define RTC_PUDR 0x64 /* RTC Pull-up Disable Register */
-#define RTC_PUSR 0x68 /* RTC Pull-up Status Register */
- /* 0x6c reserved */
-#define RTC_ASR 0x70 /* RTC Peripheral A Select Register */
-#define RTC_BSR 0x74 /* RTC Peripheral B Select Register */
-#define RTC_ABSR 0x78 /* RTC AB Status Register */
- /* 0x7c-0x9c reserved */
-#define RTC_OWER 0xa0 /* RTC Output Write Enable Register */
-#define RTC_OWDR 0xa4 /* RTC Output Write Disable Register */
-#define RTC_OWSR 0xa8 /* RTC Output Write Status Register */
- /* 0xac reserved */
+#define RTC_CR 0x00 /* RTC Control Register */
+#define RTC_MR 0x04 /* RTC Mode Register */
+#define RTC_TIMR 0x08 /* RTC Time Register */
+#define RTC_CALR 0x0c /* RTC Calendar Register */
+#define RTC_TIMALR 0x10 /* RTC Time Alarm Register */
+#define RTC_CALALR 0x14 /* RTC Calendar Alarm Register */
+#define RTC_SR 0x18 /* RTC Status Register */
+#define RTC_SCCR 0x1c /* RTC Status Command Clear Register */
+#define RTC_IER 0x20 /* RTC Interrupt Enable Register */
+#define RTC_IDR 0x24 /* RTC Interrupt Disable Register */
+#define RTC_IMR 0x28 /* RTC Interrupt Mask Register */
+#define RTC_VER 0x2c /* RTC Valid Entry Register */
+
+/* TIMR */
+#define RTC_TIMR_SEC_M 0x7fUL
+#define RTC_TIMR_SEC_S 0
+#define RTC_TIMR_SEC(x) FROMBCD(((x) & RTC_TIMR_SEC_M) >> RTC_TIMR_SEC_S)
+#define RTC_TIMR_MIN_M 0x7f00UL
+#define RTC_TIMR_MIN_S 8
+#define RTC_TIMR_MIN(x) FROMBCD(((x) & RTC_TIMR_MIN_M) >> RTC_TIMR_MIN_S)
+#define RTC_TIMR_HR_M 0x3f0000UL
+#define RTC_TIMR_HR_S 16
+#define RTC_TIMR_HR(x) FROMBCD(((x) & RTC_TIMR_HR_M) >> RTC_TIMR_HR_S)
+#define RTC_TIMR_MK(hr, min, sec) \
+ ((TOBCD(hr) << RTC_TIMR_HR_S) | \
+ (TOBCD(min) << RTC_TIMR_MIN_S) | \
+ (TOBCD(sec) << RTC_TIMR_SEC_S))
+#define RTC_TIMR_PM (1UL << 22)
+
+/* CALR */
+#define RTC_CALR_CEN_M 0x0000007fUL
+#define RTC_CALR_CEN_S 0
+#define RTC_CALR_CEN(x) FROMBCD(((x) & RTC_CALR_CEN_M) >> RTC_CALR_CEN_S)
+#define RTC_CALR_YEAR_M 0x0000ff00UL
+#define RTC_CALR_YEAR_S 8
+#define RTC_CALR_YEAR(x) FROMBCD(((x) & RTC_CALR_YEAR_M) >> RTC_CALR_YEAR_S)
+#define RTC_CALR_MON_M 0x001f0000UL
+#define RTC_CALR_MON_S 16
+#define RTC_CALR_MON(x) FROMBCD(((x) & RTC_CALR_MON_M) >> RTC_CALR_MON_S)
+#define RTC_CALR_DOW_M 0x00d0000UL
+#define RTC_CALR_DOW_S 21
+#define RTC_CALR_DOW(x) FROMBCD(((x) & RTC_CALR_DOW_M) >> RTC_CALR_DOW_S)
+#define RTC_CALR_DAY_M 0x3f00000UL
+#define RTC_CALR_DAY_S 24
+#define RTC_CALR_DAY(x) FROMBCD(((x) & RTC_CALR_DAY_M) >> RTC_CALR_DAY_S)
+#define RTC_CALR_MK(yr, mon, day, dow) \
+ ((TOBCD((yr) / 100 + 19) << RTC_CALR_CENTURY_S) | \
+ (TOBCD((yr) % 100) << RTC_CALR_YEAR_S) | \
+ (TOBCD(mon) << RTC_CALR_MON_S) | \
+ (TOBCD(dow) << RTC_CALR_DOW_S) | \
+ (TOBCD(day) << RTC_CALR_DAY_S))
#endif /* ARM_AT91_AT91_RTCREG_H */
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