PERFORCE change 102573 for review

Olivier Houchard cognet at FreeBSD.org
Thu Jul 27 16:55:21 UTC 2006


http://perforce.freebsd.org/chv.cgi?CH=102573

Change 102573 by cognet at cognet on 2006/07/27 16:55:20

	More PCI init stuff, from NetBSD.

Affected files ...

.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#7 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#7 (text+ko) ====

@@ -97,6 +97,7 @@
 ixppcib_attach(device_t dev)
 {
 	int rid;
+	uint32_t reg;
 	struct ixppcib_softc *sc;
 
 	sc = device_get_softc(dev);
@@ -145,6 +146,51 @@
 	}
 
 	device_add_child(dev, "pci", -1);
+	/*
+	 * PCI->AHB address translation
+	 * 	begin at the physical memory start + OFFSET
+	 */
+#define	AHB_OFFSET	0x10000000UL
+	reg  = (AHB_OFFSET + 0x00000000) >> 0;
+	reg |= (AHB_OFFSET + 0x01000000) >> 8;
+	reg |= (AHB_OFFSET + 0x02000000) >> 16;
+	reg |= (AHB_OFFSET + 0x03000000) >> 24;
+	PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg);
+	
+#define IXPPCIB_WRITE_CONF(sc, reg, val) \
+	ixppcib_write_config(dev, 0, 0, 0, (reg), (val), 4)
+	/* Write Mapping registers PCI Configuration Registers */
+	/* Base Address 0 - 3 */
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
+	
+	/* Base Address 4 */
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
+	
+	/* Base Address 5 */
+	IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
+	
+	/* Assert some PCI errors */
+	PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
+	
+	/*
+	 * Set up byte lane swapping between little-endian PCI
+	 * and the big-endian AHB bus
+	 */
+	PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
+	
+	/*
+	 * Enable bus mastering and I/O,memory access
+	 */
+	IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
+	    PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+	
+	/*
+	 * Wait some more to ensure PCI devices have stabilised.
+	 */
+	DELAY(50000);
 
 	return (bus_generic_attach(dev));
 }


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