PERFORCE change 102504 for review

[Olivier Houchard]

http://perforce.freebsd.org/chv.cgi?CH=102504

Change 102504 by cognet at cognet on 2006/07/26 22:37:15

	Bring in PCI IRQ routing support. Largely untested.
	Obtained from:	NetBSD

Affected files ...

.. //depot/projects/arm/src/sys/arm/xscale/ixp425/files.avila#2 edit
.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixdp425_pci.c#1 add
.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixdp425reg.h#1 add
.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425.c#8 edit
.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#2 edit
.. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425var.h#4 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/xscale/ixp425/files.avila#2 (text+ko) ====

@@ -1,2 +1,3 @@
 #$FreeBSD$
 arm/xscale/ixp425/avila_machdep.c	standard
+arm/xscale/ixp425/ixdp425_pci.c		optional	pci

==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425.c#8 (text+ko) ====

@@ -103,11 +103,34 @@
 	return (0);
 }
 
+static __inline u_int32_t
+ixp425_irq2gpio_bit(int irq)
+{
+
+	static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = {
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* INT#0 -> INT#5 */
+		0x00, 0x01,				/* GPIO#0 -> GPIO#1 */
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* INT#8 -> INT#13 */
+		0xff, 0xff, 0xff, 0xff, 0xff,		/* INT#14 -> INT#18 */
+		0x02, 0x03, 0x04, 0x05, 0x06, 0x07,	/* GPIO#2 -> GPIO#7 */
+		0x08, 0x09, 0x0a, 0x0b, 0x0c,		/* GPIO#8 -> GPIO#12 */
+		0xff, 0xff				/* INT#30 -> INT#31 */
+	};
+
+	return (1U << int2gpio[irq]);
+}
+
 void
 arm_mask_irq(uintptr_t nb)
 {
 	intr_enabled &= ~(1 << nb);
 	ixp425_set_intrmask();
+	/*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/
+	if ((1 << nb) & IXP425_INT_GPIOMASK)
+		IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
+		    ixp425_irq2gpio_bit(nb);
+
+		
 }
 
 void
@@ -206,6 +229,9 @@
 	device_add_child(dev, "pcib", 0);
 	device_add_child(dev, "ixpclk", 0);
 
+	if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
+	    0, &sc->sc_gpio_ioh))
+		panic("ixp425_attach: unable to map GPIO registers");
 	bus_generic_probe(dev);
 	bus_generic_attach(dev);
 

==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#2 (text+ko) ====

@@ -124,6 +124,7 @@
 	if (sc->sc_csr == NULL)
 		panic("cannot allocate PCI CSR registers");
 
+	ixp425_md_attach(dev);
 	/* always setup the base, incase another OS messes w/ it */
 	PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
 
@@ -377,12 +378,10 @@
 }
 
 static int
-ixppcib_route_interrupt(device_t bridge, device_t dev, int pin)
+ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
 {
 
-	device_printf(bridge, "routing pin %d for %s\n", pin,
-	    device_get_nameunit(dev));
-	return (pin);
+	return (ixp425_md_route_interrupt(bridge, device, pin));
 }
 
 static device_method_t ixppcib_methods[] = {

==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425var.h#4 (text+ko) ====

@@ -57,6 +57,7 @@
 struct ixp425_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_gpio_ioh;
 
 	u_int32_t sc_intrmask;
 
@@ -85,4 +86,7 @@
 
 uint32_t ixp425_sdram_size(void);
 
+int	ixp425_md_route_interrupt(device_t, device_t, int);
+void	ixp425_md_attach(device_t);
+
 #endif /* _IXP425VAR_H_ */