PERFORCE change 102037 for review
Bruce M Simpson
bms at FreeBSD.org
Thu Jul 20 22:52:49 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=102037
Change 102037 by bms at bms_empiric on 2006/07/20 22:51:50
Put back old definitions that were blown away.
Propagate change to consumers.
Affected files ...
.. //depot/projects/mips2/src/sys/mips/include/cpuregs.h#7 integrate
.. //depot/projects/mips2/src/sys/mips/mips/cpu.c#13 integrate
.. //depot/projects/mips2/src/sys/mips/mips/exception.S#6 integrate
.. //depot/projects/mips2/src/sys/mips/mips/trap.c#5 integrate
Differences ...
==== //depot/projects/mips2/src/sys/mips/include/cpuregs.h#7 (text+ko) ====
@@ -64,13 +64,15 @@
/*
* Address space.
- * MIPS32 CPUs partition their 32-bit address space into four segments:
+ * 32-bit mips CPUS partition their 32-bit address space into four segments:
*
* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
*
+ * mips1 physical memory is limited to 512Mbytes, which is
+ * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
* Caching of mapped addresses is controlled by bits in the TLB entry.
*/
@@ -91,48 +93,180 @@
#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
-#define MIPS_VA_TO_CINDEX(x) \
+#define MIPS3_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
+#define MIPS_PHYS_TO_XKPHYS(cca,x) \
+ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
+#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
+
/* CPU dependent mtc0 hazard hook */
#define COP0_SYNC /* nothing */
#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
/*
- * Cause register bit assignments.
+ * The bits in the cause register.
+ *
+ * Bits common to r3000 and r4000:
+ *
+ * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
+ * MIPS_CR_COP_ERR Coprocessor error.
+ * MIPS_CR_IP Interrupt pending bits defined below.
+ * (same meaning as in CAUSE register).
+ * MIPS_CR_EXC_CODE The exception type (see exception codes below).
+ *
+ * Differences:
+ * r3k has 4 bits of execption type, r4k has 5 bits.
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
-#define MIPS_CR_EXC_CODE 0x0000007C
+#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
+#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
/*
- * Status register bit assignments.
+ * The bits in the status register. All bits are active when set to 1.
+ *
+ * R3000 status register fields:
+ * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
+ * MIPS_SR_TS TLB shutdown.
+ *
+ * MIPS_SR_INT_IE Master (current) interrupt enable bit.
+ *
+ * Differences:
+ * r3k has cache control is via frobbing SR register bits, whereas the
+ * r4k cache control is via explicit instructions.
+ * r3k has a 3-entry stack of kernel/user bits, whereas the
+ * r4k has kernel/supervisor/user.
*/
#define MIPS_SR_COP_USABILITY 0xf0000000
#define MIPS_SR_COP_0_BIT 0x10000000
#define MIPS_SR_COP_1_BIT 0x20000000
-#define MIPS_SR_RP 0x08000000 /* Optional: reduced power mode */
-#define MIPS_SR_FR 0x04000000 /* 64-bit capable fpu */
-#define MIPS_SR_RE 0x02000000 /* Optional: reverse user endian */
+
+ /* r4k and r3k differences, see below */
+
#define MIPS_SR_MX 0x01000000 /* MIPS64 */
#define MIPS_SR_PX 0x00800000 /* MIPS64 */
#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
-#define MIPS_SR_TS 0x00200000 /* TLB matched multiple entries */
-#define MIPS_SR_SOFT_RESET 0x00100000 /* Optional: soft reset occurred */
-#define MIPS_SR_NMI 0x00080000 /* Optional: NMI occurred */
-#define MIPS_SR_INT_MASK 0x0000ff00
-#define MIPS_SR_KX 0x00000080 /* MIPS64 */
-#define MIPS_SR_SX 0x00000040 /* MIPS64 */
-#define MIPS_SR_UX 0x00000020 /* MIPS64 */
-#define MIPS_SR_KSU_MASK 0x00000018 /* privilege mode */
-#define MIPS_SR_KSU_USER 0x00000010
-#define MIPS_SR_KSU_SUPER 0x00000008
-#define MIPS_SR_KSU_KERNEL 0x00000000
-#define MIPS_SR_ERL 0x00000004 /* error level */
-#define MIPS_SR_EXL 0x00000002 /* exception level */
+#define MIPS_SR_TS 0x00200000
+
#define MIPS_SR_INT_IE 0x00000001
+/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
+/*#define MIPS_SR_INT_MASK 0x0000ff00*/
+
+/*
+ * The R2000/R3000-specific status register bit definitions.
+ * all bits are active when set to 1.
+ *
+ * MIPS_SR_PARITY_ERR Parity error.
+ * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
+ * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
+ * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
+ * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
+ * Interrupt enable bits defined below.
+ * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
+ * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
+ * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
+ * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
+ * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
+ */
+
+#define MIPS1_PARITY_ERR 0x00100000
+#define MIPS1_CACHE_MISS 0x00080000
+#define MIPS1_PARITY_ZERO 0x00040000
+#define MIPS1_SWAP_CACHES 0x00020000
+#define MIPS1_ISOL_CACHES 0x00010000
+
+#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
+#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
+#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
+
+/* backwards compatibility */
+#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
+#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
+#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
+#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
+#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
+
+#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
+#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
+#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
+#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
+#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
+
+/*
+ * R4000 status register bit definitons,
+ * where different from r2000/r3000.
+ */
+#define MIPS3_SR_XX 0x80000000
+#define MIPS3_SR_RP 0x08000000
+#define MIPS3_SR_FR 0x04000000
+#define MIPS3_SR_RE 0x02000000
+
+#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
+#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
+#define MIPS3_SR_SR 0x00100000
+#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
+#define MIPS3_SR_DIAG_CH 0x00040000
+#define MIPS3_SR_DIAG_CE 0x00020000
+#define MIPS3_SR_DIAG_PE 0x00010000
+#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
+#define MIPS3_SR_KX 0x00000080
+#define MIPS3_SR_SX 0x00000040
+#define MIPS3_SR_UX 0x00000020
+#define MIPS3_SR_KSU_MASK 0x00000018
+#define MIPS3_SR_KSU_USER 0x00000010
+#define MIPS3_SR_KSU_SUPER 0x00000008
+#define MIPS3_SR_KSU_KERNEL 0x00000000
+#define MIPS3_SR_ERL 0x00000004
+#define MIPS3_SR_EXL 0x00000002
+
+#ifdef MIPS3_5900
+#undef MIPS_SR_INT_IE
+#define MIPS_SR_INT_IE 0x00010001 /* XXX */
+#endif
+
+/*
+ * These definitions are for MIPS32 processors.
+ */
+#define MIPS32_SR_RP 0x08000000 /* reduced power mode */
+#define MIPS32_SR_FR 0x04000000 /* 64-bit capable fpu */
+#define MIPS32_SR_RE 0x02000000 /* reverse user endian */
+#define MIPS32_SR_MX 0x01000000 /* MIPS64 */
+#define MIPS32_SR_PX 0x00800000 /* MIPS64 */
+#define MIPS32_SR_BEV 0x00400000 /* Use boot exception vector */
+#define MIPS32_SR_TS 0x00200000 /* TLB multiple match */
+#define MIPS32_SR_SOFT_RESET 0x00100000 /* soft reset occurred */
+#define MIPS32_SR_NMI 0x00080000 /* NMI occurred */
+#define MIPS32_SR_INT_MASK 0x0000ff00
+#define MIPS32_SR_KX 0x00000080 /* MIPS64 */
+#define MIPS32_SR_SX 0x00000040 /* MIPS64 */
+#define MIPS32_SR_UX 0x00000020 /* MIPS64 */
+#define MIPS32_SR_KSU_MASK 0x00000018 /* privilege mode */
+#define MIPS32_SR_KSU_USER 0x00000010
+#define MIPS32_SR_KSU_SUPER 0x00000008
+#define MIPS32_SR_KSU_KERNEL 0x00000000
+#define MIPS32_SR_ERL 0x00000004 /* error level */
+#define MIPS32_SR_EXL 0x00000002 /* exception level */
+
+#define MIPS_SR_SOFT_RESET MIPS3_SR_SR
+#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
+#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
+#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
+#define MIPS_SR_KX MIPS3_SR_KX
+#define MIPS_SR_SX MIPS3_SR_SX
+#define MIPS_SR_UX MIPS3_SR_UX
+
+#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
+#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
+#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
+#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
+#define MIPS_SR_ERL MIPS3_SR_ERL
+#define MIPS_SR_EXL MIPS3_SR_EXL
+
/*
* The interrupt masks.
@@ -150,24 +284,25 @@
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
- * MIPS32 CPUs have an on-chip timer at INT_MASK_5.
- * Routing of this interrupt is optional; MIPS32 rev2
- * changes its semantics.
- * See section 8.16 of the MIPS32 PRA spec for more info.
+ * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
+ * choose to enable this interrupt.
*/
-#if defined(MIPS32_ENABLE_CLOCK_INTR)
-#define MIPS32_INT_MASK MIPS_INT_MASK
-#define MIPS32_HARD_INT_MASK MIPS_HARD_INT_MASK
+#if defined(MIPS3_ENABLE_CLOCK_INTR)
+#define MIPS3_INT_MASK MIPS_INT_MASK
+#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
#else
-#define MIPS32_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
-#define MIPS32_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
#endif
/*
- * The bits in the MIPS32 context register.
+ * The bits in the context register.
*/
-#define MIPS_CNTXT_PTE_BASE 0xFF800000
-#define MIPS_CNTXT_BAD_VPN2 0x007FFFF0
+#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
+#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
+
+#define MIPS3_CNTXT_PTE_BASE 0xFF800000
+#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
/*
* Location of MIPS32 exception vectors. Most are multiplexed in
@@ -186,6 +321,144 @@
#define MIPS_VEC_INTERRUPT 0x80000200
/*
+ * The bits in the MIPS3 config register.
+ *
+ * bit 0..5: R/W, Bit 6..31: R/O
+ */
+
+/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+#define MIPS3_CONFIG_K0_MASK 0x00000007
+
+/*
+ * R/W Update on Store Conditional
+ * 0: Store Conditional uses coherency algorithm specified by TLB
+ * 1: Store Conditional uses cacheable coherent update on write
+ */
+#define MIPS3_CONFIG_CU 0x00000008
+
+#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
+#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
+#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
+ (((config) & (bit)) ? 32 : 16)
+
+#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
+#define MIPS3_CONFIG_DC_SHIFT 6
+#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
+#define MIPS3_CONFIG_IC_SHIFT 9
+#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
+
+/* Cache size mode indication: available only on Vr41xx CPUs */
+#define MIPS3_CONFIG_CS 0x00001000
+#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
+#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+ ((base) << (((config) & (mask)) >> (shift)))
+
+/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
+#define MIPS3_CONFIG_SE 0x00001000
+
+/* Block ordering: 0: sequential, 1: sub-block */
+#define MIPS3_CONFIG_EB 0x00002000
+
+/* ECC mode - 0: ECC mode, 1: parity mode */
+#define MIPS3_CONFIG_EM 0x00004000
+
+/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
+#define MIPS3_CONFIG_BE 0x00008000
+
+/* Dirty Shared coherency state - 0: enabled, 1: disabled */
+#define MIPS3_CONFIG_SM 0x00010000
+
+/* Secondary Cache - 0: present, 1: not present */
+#define MIPS3_CONFIG_SC 0x00020000
+
+/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
+#define MIPS3_CONFIG_EW_MASK 0x000c0000
+#define MIPS3_CONFIG_EW_SHIFT 18
+
+/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
+#define MIPS3_CONFIG_SW 0x00100000
+
+/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
+#define MIPS3_CONFIG_SS 0x00200000
+
+/* Secondary Cache line size */
+#define MIPS3_CONFIG_SB_MASK 0x00c00000
+#define MIPS3_CONFIG_SB_SHIFT 22
+#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
+ (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
+
+/* Write back data rate */
+#define MIPS3_CONFIG_EP_MASK 0x0f000000
+#define MIPS3_CONFIG_EP_SHIFT 24
+
+/* System clock ratio - this value is CPU dependent */
+#define MIPS3_CONFIG_EC_MASK 0x70000000
+#define MIPS3_CONFIG_EC_SHIFT 28
+
+/* Master-Checker Mode - 1: enabled */
+#define MIPS3_CONFIG_CM 0x80000000
+
+/*
+ * The bits in the MIPS4 config register.
+ */
+
+/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
+#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
+#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
+#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
+#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
+#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
+#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
+#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
+#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
+#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
+#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
+#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
+#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
+#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
+
+#define MIPS4_CONFIG_DC_SHIFT 26
+#define MIPS4_CONFIG_IC_SHIFT 29
+
+#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+ ((base) << (((config) & (mask)) >> (shift)))
+
+#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
+ (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
+
+/*
+ * Location of exception vectors.
+ *
+ * Common vectors: reset and UTLB miss.
+ */
+#define MIPS_RESET_EXC_VEC 0xBFC00000
+#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
+
+/*
+ * MIPS-1 general exception vector (everything else)
+ */
+#define MIPS1_GEN_EXC_VEC 0x80000080
+
+/*
+ * MIPS-III exception vectors
+ */
+#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
+#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
+#define MIPS3_GEN_EXC_VEC 0x80000180
+
+/*
+ * TX79 (R5900) exception vectors
+ */
+#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
+#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
+
+/*
+ * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
+ */
+#define MIPS3_INTR_EXC_VEC 0x80000200
+
+/*
* Coprocessor 0 registers:
*
* v--- width for mips I,III,32,64
@@ -238,9 +511,13 @@
#define _(n) n
#endif
+
#define MIPS_COP_0_TLB_INDEX _(0)
#define MIPS_COP_0_TLB_RANDOM _(1)
+ /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
+
#define MIPS_COP_0_TLB_CONTEXT _(4)
+ /* $5 and $6 new with MIPS-III */
#define MIPS_COP_0_BAD_VADDR _(8)
#define MIPS_COP_0_TLB_HI _(10)
#define MIPS_COP_0_STATUS _(12)
@@ -248,6 +525,11 @@
#define MIPS_COP_0_EXC_PC _(14)
#define MIPS_COP_0_PRID _(15)
+
+/* MIPS-I */
+#define MIPS_COP_0_TLB_LOW _(2)
+
+/* MIPS-III */
#define MIPS_COP_0_TLB_LO0 _(2)
#define MIPS_COP_0_TLB_LO1 _(3)
@@ -282,17 +564,10 @@
#define MIPS_MMU_BAT 0x02 /* Standard BAT */
#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
-#define MIPS_CONFIG_CM 0x80000000 /* next selection is present */
-
-#define MIPS_CONFIG0_K23_MASK 0x70000000 /* kseg2/3 coherency mode */
-#define MIPS_CONFIG0_KU_MASK 0x0E000000 /* kuseg coherency mode */
-#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
-#define MIPS_CONFIG0_AT_MASK 0x00006000 /* architecture type (MIPS32/64) */
-#define MIPS_CONFIG0_AR_MASK 0x00001C00 /* architecture revision */
#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
#define MIPS_CONFIG0_MT_SHIFT 7
-#define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */
-#define MIPS_CONFIG0_K0_MASK 0x00000007 /* kseg0 coherency mode */
+#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
+#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */
#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
#define MIPS_CONFIG1_TLBSZ_SHIFT 25
@@ -392,6 +667,12 @@
/*
* The low part of the TLB entry.
*/
+#define MIPS1_TLB_PFN 0xfffff000
+#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
+#define MIPS1_TLB_DIRTY_BIT 0x00000400
+#define MIPS1_TLB_VALID_BIT 0x00000200
+#define MIPS1_TLB_GLOBAL_BIT 0x00000100
+
#define MIPS3_TLB_PFN 0x3fffffc0
#define MIPS3_TLB_ATTR_MASK 0x00000038
#define MIPS3_TLB_ATTR_SHIFT 3
@@ -399,8 +680,11 @@
#define MIPS3_TLB_VALID_BIT 0x00000002
#define MIPS3_TLB_GLOBAL_BIT 0x00000001
+#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
+#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
+#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
/*
@@ -427,32 +711,54 @@
/*
* The high part of the TLB entry.
*/
+#define MIPS1_TLB_VPN 0xfffff000
+#define MIPS1_TLB_PID 0x00000fc0
+#define MIPS1_TLB_PID_SHIFT 6
+
#define MIPS3_TLB_VPN2 0xffffe000
#define MIPS3_TLB_ASID 0x000000ff
+#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
#define MIPS3_TLB_PID MIPS3_TLB_ASID
#define MIPS_TLB_VIRT_PAGE_SHIFT 12
/*
+ * r3000: shift count to put the index in the right spot.
+ */
+#define MIPS1_TLB_INDEX_SHIFT 8
+
+/*
* The first TLB that write random hits.
*/
+#define MIPS1_TLB_FIRST_RAND_ENTRY 8
#define MIPS3_TLB_WIRED_UPAGES 1
/*
* The number of process id entries.
*/
+#define MIPS1_TLB_NUM_PIDS 64
#define MIPS3_TLB_NUM_ASIDS 256
/*
* Patch codes to hide CPU design differences between MIPS1 and MIPS3.
*/
+
+/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
+
+#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
+ && defined(MIPS1) /* XXX simonb must be neater! */
+#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
+#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
+#endif
+
#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
&& !defined(MIPS1) /* XXX simonb must be neater! */
#define MIPS_TLB_PID_SHIFT 0
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
#endif
+
#if !defined(MIPS_TLB_PID_SHIFT)
#define MIPS_TLB_PID_SHIFT \
((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
@@ -497,15 +803,29 @@
#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
/*
- * CPU revision IDs.
+ * CPU revision IDs for some prehistoric processors.
*/
+/* For MIPS_R3000 */
+#define MIPS_REV_R3000 0x20
+#define MIPS_REV_R3000A 0x30
+
+/* For MIPS_TX3900 */
+#define MIPS_REV_TX3912 0x10
+#define MIPS_REV_TX3922 0x30
+#define MIPS_REV_TX3927 0x40
+
/* For MIPS_R4000 */
+#define MIPS_REV_R4000_A 0x00
+#define MIPS_REV_R4000_B 0x22
#define MIPS_REV_R4000_C 0x30
#define MIPS_REV_R4400_A 0x40
#define MIPS_REV_R4400_B 0x50
#define MIPS_REV_R4400_C 0x60
+/* For MIPS_TX4900 */
+#define MIPS_REV_TX4927 0x22
+
/*
* CPU processor revision IDs for company ID == 1 (MIPS)
*/
@@ -560,4 +880,14 @@
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
+#ifdef ENABLE_MIPS_TX3900
+#include <mips/r3900regs.h>
+#endif
+#ifdef MIPS3_5900
+#include <mips/r5900regs.h>
+#endif
+#ifdef MIPS64_SB1
+#include <mips/sb1regs.h>
+#endif
+
#endif /* _MIPS_CPUREGS_H_ */
==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#13 (text+ko) ====
@@ -134,7 +134,7 @@
cpuinfo->tlb_type = ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT);
/* If config register selection 1 does not exist, exit. */
- if (!(cfg0 & MIPS_CONFIG_CM))
+ if (!(cfg0 & MIPS3_CONFIG_CM))
return;
/* Learn TLB size and L1 cache geometry. */
==== //depot/projects/mips2/src/sys/mips/mips/exception.S#6 (text+ko) ====
@@ -23,7 +23,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#5 $
+ * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#6 $
*/
#include "opt_ddb.h"
@@ -94,7 +94,7 @@
.set noat
mfc0 k0, MIPS_COP_0_CAUSE
- and k0, MIPS_CR_EXC_CODE
+ and k0, MIPS3_CR_EXC_CODE
srl k0, MIPS_CR_EXC_CODE_SHIFT
sll k0, 3 /* Index 64-bits. */
la k1, ExceptionHandlerTable
@@ -139,7 +139,7 @@
*/
mfc0 a1, MIPS_COP_0_CAUSE
- and k0, a1, MIPS_CR_EXC_CODE
+ and k0, a1, MIPS3_CR_EXC_CODE
bnez k0, 1f
move a0, k1
==== //depot/projects/mips2/src/sys/mips/mips/trap.c#5 (text+ko) ====
@@ -107,7 +107,7 @@
tf = retf;
bcopy(retf, tf, sizeof *tf);
- code = (cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
+ code = (cause & MIPS3_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
kernelmode = (tf->tf_regs[TF_SR] & MIPS_SR_KSU_USER) == 0;
/*
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