PERFORCE change 101793 for review
Bruce M Simpson
bms at FreeBSD.org
Mon Jul 17 19:43:12 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=101793
Change 101793 by bms at bms_montagne on 2006/07/17 19:43:03
Integrate from bms_mips:
Remove legacy MIPS defines.
Add a function for obtaining the CONFIG register's
multiple selections.
Add MIPS64 trap definitions.
Clean up cpu.c and add a function to identify
cache geometry and CPU vendor, etc.
Merge YAMON environment vector stuff.
Style fixes.
Affected files ...
.. //depot/projects/mips2/src/sys/mips/include/cpufunc.h#14 integrate
.. //depot/projects/mips2/src/sys/mips/include/cpuinfo.h#2 integrate
.. //depot/projects/mips2/src/sys/mips/include/cpuregs.h#5 integrate
.. //depot/projects/mips2/src/sys/mips/include/trap.h#3 integrate
.. //depot/projects/mips2/src/sys/mips/mips/cpu.c#11 integrate
.. //depot/projects/mips2/src/sys/mips/mips/exception.S#4 integrate
.. //depot/projects/mips2/src/sys/mips/mips/locore.S#12 integrate
.. //depot/projects/mips2/src/sys/mips/mips/machdep.c#17 integrate
.. //depot/projects/mips2/src/sys/mips/mips/tick.c#2 integrate
.. //depot/projects/mips2/src/sys/mips/mips/trap.c#4 integrate
.. //depot/projects/mips2/src/sys/mips/mips4k/malta/files.malta#4 integrate
.. //depot/projects/mips2/src/sys/mips/mips4k/malta/yamon.c#1 branch
Differences ...
==== //depot/projects/mips2/src/sys/mips/include/cpufunc.h#14 (text+ko) ====
@@ -167,16 +167,23 @@
MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
-/*
- * XXXMIPS: I think this change was brought by bms at .
- */
-/* XXX: mips32 */
+/* XXX: Some of these registers are specific to MIPS32. */
MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
-/* xcontext does not exist on mips32 */
+MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
+
+static __inline u_int32_t
+mips_rd_config_sel1(void)
+{
+ int v0;
+ __asm __volatile("mfc0 %[v0], $16, 1 ;"
+ : [v0] "=&r" (v0));
+ mips_barrier();
+ return (v0);
+}
#undef MIPS_RDRW32_COP0
==== //depot/projects/mips2/src/sys/mips/include/cpuinfo.h#2 (text+ko) ====
@@ -48,6 +48,24 @@
#ifdef _KERNEL
#ifndef LOCORE
+struct mips_cpuinfo {
+ u_int8_t cpu_vendor;
+ u_int8_t cpu_rev;
+ u_int8_t cpu_impl;
+ u_int8_t tlb_type;
+ u_int16_t tlb_nentries;
+ struct {
+ u_int8_t ic_linesize;
+ u_int8_t ic_nways;
+ u_int16_t ic_nsets;
+ u_int8_t dc_linesize;
+ u_int8_t dc_nways;
+ u_int16_t dc_nsets;
+ } l1;
+};
+
+/* TODO: Merge above structure with NetBSD's below. */
+
struct cpu_info {
#ifdef notyet
struct schedstate_percpu ci_schedstate; /* scheduler state */
==== //depot/projects/mips2/src/sys/mips/include/cpuregs.h#5 (text+ko) ====
@@ -64,15 +64,13 @@
/*
* Address space.
- * 32-bit mips CPUS partition their 32-bit address space into four segments:
+ * MIPS32 CPUs partition their 32-bit address space into four segments:
*
* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
*
- * mips1 physical memory is limited to 512Mbytes, which is
- * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
* Caching of mapped addresses is controlled by bits in the TLB entry.
*/
@@ -93,162 +91,50 @@
#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
-#define MIPS3_VA_TO_CINDEX(x) \
+#define MIPS_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
-#define MIPS_PHYS_TO_XKPHYS(cca,x) \
- ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
-#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
-
/* CPU dependent mtc0 hazard hook */
#define COP0_SYNC /* nothing */
#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
/*
- * The bits in the cause register.
- *
- * Bits common to r3000 and r4000:
- *
- * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
- * MIPS_CR_COP_ERR Coprocessor error.
- * MIPS_CR_IP Interrupt pending bits defined below.
- * (same meaning as in CAUSE register).
- * MIPS_CR_EXC_CODE The exception type (see exception codes below).
- *
- * Differences:
- * r3k has 4 bits of execption type, r4k has 5 bits.
+ * Cause register bit assignments.
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
-#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
-#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
+#define MIPS_CR_EXC_CODE 0x0000007C
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
/*
- * The bits in the status register. All bits are active when set to 1.
- *
- * R3000 status register fields:
- * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
- * MIPS_SR_TS TLB shutdown.
- *
- * MIPS_SR_INT_IE Master (current) interrupt enable bit.
- *
- * Differences:
- * r3k has cache control is via frobbing SR register bits, whereas the
- * r4k cache control is via explicit instructions.
- * r3k has a 3-entry stack of kernel/user bits, whereas the
- * r4k has kernel/supervisor/user.
+ * Status register bit assignments.
*/
#define MIPS_SR_COP_USABILITY 0xf0000000
#define MIPS_SR_COP_0_BIT 0x10000000
#define MIPS_SR_COP_1_BIT 0x20000000
-
- /* r4k and r3k differences, see below */
-
+#define MIPS_SR_RP 0x08000000 /* Optional: reduced power mode */
+#define MIPS_SR_FR 0x04000000 /* 64-bit capable fpu */
+#define MIPS_SR_RE 0x02000000 /* Optional: reverse user endian */
#define MIPS_SR_MX 0x01000000 /* MIPS64 */
#define MIPS_SR_PX 0x00800000 /* MIPS64 */
#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
-#define MIPS_SR_TS 0x00200000
-
- /* r4k and r3k differences, see below */
-
+#define MIPS_SR_TS 0x00200000 /* TLB matched multiple entries */
+#define MIPS_SR_SOFT_RESET 0x00100000 /* Optional: soft reset occurred */
+#define MIPS_SR_NMI 0x00080000 /* Optional: NMI occurred */
+#define MIPS_SR_INT_MASK 0x0000ff00
+#define MIPS_SR_KX 0x00000080 /* MIPS64 */
+#define MIPS_SR_SX 0x00000040 /* MIPS64 */
+#define MIPS_SR_UX 0x00000020 /* MIPS64 */
+#define MIPS_SR_KSU_MASK 0x00000018 /* privilege mode */
+#define MIPS_SR_KSU_USER 0x00000010
+#define MIPS_SR_KSU_SUPER 0x00000008
+#define MIPS_SR_KSU_KERNEL 0x00000000
+#define MIPS_SR_ERL 0x00000004 /* error level */
+#define MIPS_SR_EXL 0x00000002 /* exception level */
#define MIPS_SR_INT_IE 0x00000001
-/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
-/*#define MIPS_SR_INT_MASK 0x0000ff00*/
-
-
-/*
- * The R2000/R3000-specific status register bit definitions.
- * all bits are active when set to 1.
- *
- * MIPS_SR_PARITY_ERR Parity error.
- * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
- * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
- * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
- * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
- * Interrupt enable bits defined below.
- * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
- * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
- * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
- * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
- * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
- */
-
-#define MIPS1_PARITY_ERR 0x00100000
-#define MIPS1_CACHE_MISS 0x00080000
-#define MIPS1_PARITY_ZERO 0x00040000
-#define MIPS1_SWAP_CACHES 0x00020000
-#define MIPS1_ISOL_CACHES 0x00010000
-
-#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
-#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
-#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
-#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
-#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
-
-/* backwards compatibility */
-#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
-#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
-#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
-#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
-#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
-
-#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
-#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
-#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
-#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
-#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
/*
- * R4000 status register bit definitons,
- * where different from r2000/r3000.
- */
-#define MIPS3_SR_XX 0x80000000
-#define MIPS3_SR_RP 0x08000000
-#define MIPS3_SR_FR 0x04000000
-#define MIPS3_SR_RE 0x02000000
-
-#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
-#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
-#define MIPS3_SR_SR 0x00100000
-#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
-#define MIPS3_SR_DIAG_CH 0x00040000
-#define MIPS3_SR_DIAG_CE 0x00020000
-#define MIPS3_SR_DIAG_PE 0x00010000
-#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
-#define MIPS3_SR_KX 0x00000080
-#define MIPS3_SR_SX 0x00000040
-#define MIPS3_SR_UX 0x00000020
-#define MIPS3_SR_KSU_MASK 0x00000018
-#define MIPS3_SR_KSU_USER 0x00000010
-#define MIPS3_SR_KSU_SUPER 0x00000008
-#define MIPS3_SR_KSU_KERNEL 0x00000000
-#define MIPS3_SR_ERL 0x00000004
-#define MIPS3_SR_EXL 0x00000002
-
-#ifdef MIPS3_5900
-#undef MIPS_SR_INT_IE
-#define MIPS_SR_INT_IE 0x00010001 /* XXX */
-#endif
-
-#define MIPS_SR_SOFT_RESET MIPS3_SR_SR
-#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
-#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
-#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
-#define MIPS_SR_KX MIPS3_SR_KX
-#define MIPS_SR_SX MIPS3_SR_SX
-#define MIPS_SR_UX MIPS3_SR_UX
-
-#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
-#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
-#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
-#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
-#define MIPS_SR_ERL MIPS3_SR_ERL
-#define MIPS_SR_EXL MIPS3_SR_EXL
-
-
-/*
* The interrupt masks.
* If a bit in the mask is 1 then the interrupt is enabled (or pending).
*/
@@ -264,165 +150,41 @@
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
- * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
- * choose to enable this interrupt.
+ * MIPS32 CPUs have an on-chip timer at INT_MASK_5.
+ * Routing of this interrupt is optional; MIPS32 rev2
+ * changes its semantics.
+ * See section 8.16 of the MIPS32 PRA spec for more info.
*/
-#if defined(MIPS3_ENABLE_CLOCK_INTR)
-#define MIPS3_INT_MASK MIPS_INT_MASK
-#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
+#if defined(MIPS32_ENABLE_CLOCK_INTR)
+#define MIPS32_INT_MASK MIPS_INT_MASK
+#define MIPS32_HARD_INT_MASK MIPS_HARD_INT_MASK
#else
-#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
-#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS32_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS32_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
#endif
/*
- * The bits in the context register.
+ * The bits in the MIPS32 context register.
*/
-#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
-#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
+#define MIPS_CNTXT_PTE_BASE 0xFF800000
+#define MIPS_CNTXT_BAD_VPN2 0x007FFFF0
-#define MIPS3_CNTXT_PTE_BASE 0xFF800000
-#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
-
/*
- * The bits in the MIPS3 config register.
- *
- * bit 0..5: R/W, Bit 6..31: R/O
+ * Location of MIPS32 exception vectors. Most are multiplexed in
+ * the sense that further decoding is necessary (e.g. reading the
+ * CAUSE register or NMI bits in STATUS).
+ * Most interrupts go via the
+ * The INT vector is dedicated for hardware interrupts; it is
+ * only referenced if the IV bit in CAUSE is set to 1.
*/
+#define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */
+#define MIPS_VEC_EJTAG 0xBFC00480
+#define MIPS_VEC_TLB 0x80000000
+#define MIPS_VEC_CACHE 0x80000100
+#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */
+#define MIPS_VEC_INTERRUPT 0x80000200
-/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
-#define MIPS3_CONFIG_K0_MASK 0x00000007
-
/*
- * R/W Update on Store Conditional
- * 0: Store Conditional uses coherency algorithm specified by TLB
- * 1: Store Conditional uses cacheable coherent update on write
- */
-#define MIPS3_CONFIG_CU 0x00000008
-
-#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
-#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
-#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
- (((config) & (bit)) ? 32 : 16)
-
-#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
-#define MIPS3_CONFIG_DC_SHIFT 6
-#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
-#define MIPS3_CONFIG_IC_SHIFT 9
-#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
-
-/* Cache size mode indication: available only on Vr41xx CPUs */
-#define MIPS3_CONFIG_CS 0x00001000
-#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
-#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
- ((base) << (((config) & (mask)) >> (shift)))
-
-/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
-#define MIPS3_CONFIG_SE 0x00001000
-
-/* Block ordering: 0: sequential, 1: sub-block */
-#define MIPS3_CONFIG_EB 0x00002000
-
-/* ECC mode - 0: ECC mode, 1: parity mode */
-#define MIPS3_CONFIG_EM 0x00004000
-
-/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
-#define MIPS3_CONFIG_BE 0x00008000
-
-/* Dirty Shared coherency state - 0: enabled, 1: disabled */
-#define MIPS3_CONFIG_SM 0x00010000
-
-/* Secondary Cache - 0: present, 1: not present */
-#define MIPS3_CONFIG_SC 0x00020000
-
-/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
-#define MIPS3_CONFIG_EW_MASK 0x000c0000
-#define MIPS3_CONFIG_EW_SHIFT 18
-
-/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
-#define MIPS3_CONFIG_SW 0x00100000
-
-/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
-#define MIPS3_CONFIG_SS 0x00200000
-
-/* Secondary Cache line size */
-#define MIPS3_CONFIG_SB_MASK 0x00c00000
-#define MIPS3_CONFIG_SB_SHIFT 22
-#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
- (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
-
-/* Write back data rate */
-#define MIPS3_CONFIG_EP_MASK 0x0f000000
-#define MIPS3_CONFIG_EP_SHIFT 24
-
-/* System clock ratio - this value is CPU dependent */
-#define MIPS3_CONFIG_EC_MASK 0x70000000
-#define MIPS3_CONFIG_EC_SHIFT 28
-
-/* Master-Checker Mode - 1: enabled */
-#define MIPS3_CONFIG_CM 0x80000000
-
-/*
- * The bits in the MIPS4 config register.
- */
-
-/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
-#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
-#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
-#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
-#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
-#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
-#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
-#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
-#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
-#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
-#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
-#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
-#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
-#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
-#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
-
-#define MIPS4_CONFIG_DC_SHIFT 26
-#define MIPS4_CONFIG_IC_SHIFT 29
-
-#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
- ((base) << (((config) & (mask)) >> (shift)))
-
-#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
- (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
-
-/*
- * Location of exception vectors.
- *
- * Common vectors: reset and UTLB miss.
- */
-#define MIPS_RESET_EXC_VEC 0xBFC00000
-#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
-
-/*
- * MIPS-1 general exception vector (everything else)
- */
-#define MIPS1_GEN_EXC_VEC 0x80000080
-
-/*
- * MIPS-III exception vectors
- */
-#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
-#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
-#define MIPS3_GEN_EXC_VEC 0x80000180
-
-/*
- * TX79 (R5900) exception vectors
- */
-#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
-#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
-
-/*
- * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
- */
-#define MIPS3_INTR_EXC_VEC 0x80000200
-
-/*
* Coprocessor 0 registers:
*
* v--- width for mips I,III,32,64
@@ -468,22 +230,16 @@
* 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
*/
-/*
- * XXMIPS: Does LOCORE defines buy us something? Check which one is it.
- */
+/* Deal with inclusion from an assembly file. */
#if defined(_LOCORE) || defined(LOCORE)
#define _(n) $n
#else
#define _(n) n
#endif
-
#define MIPS_COP_0_TLB_INDEX _(0)
#define MIPS_COP_0_TLB_RANDOM _(1)
- /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
-
#define MIPS_COP_0_TLB_CONTEXT _(4)
- /* $5 and $6 new with MIPS-III */
#define MIPS_COP_0_BAD_VADDR _(8)
#define MIPS_COP_0_TLB_HI _(10)
#define MIPS_COP_0_STATUS _(12)
@@ -491,11 +247,6 @@
#define MIPS_COP_0_EXC_PC _(14)
#define MIPS_COP_0_PRID _(15)
-
-/* MIPS-I */
-#define MIPS_COP_0_TLB_LOW _(2)
-
-/* MIPS-III */
#define MIPS_COP_0_TLB_LO0 _(2)
#define MIPS_COP_0_TLB_LO1 _(3)
@@ -524,6 +275,47 @@
#define MIPS_COP_0_DATA_HI _(29)
#define MIPS_COP_0_DESAVE _(31)
+/* MIPS32 Config register definitions */
+#define MIPS_MMU_NONE 0x00 /* No MMU present */
+#define MIPS_MMU_TLB 0x01 /* Standard TLB */
+#define MIPS_MMU_BAT 0x02 /* Standard BAT */
+#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
+
+#define MIPS_CONFIG_CM 0x80000000 /* next selection is present */
+
+#define MIPS_CONFIG0_K23_MASK 0x70000000 /* kseg2/3 coherency mode */
+#define MIPS_CONFIG0_KU_MASK 0x0E000000 /* kuseg coherency mode */
+#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
+#define MIPS_CONFIG0_AT_MASK 0x00006000 /* architecture type (MIPS32/64) */
+#define MIPS_CONFIG0_AR_MASK 0x00001C00 /* architecture revision */
+#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
+#define MIPS_CONFIG0_MT_SHIFT 7
+#define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */
+#define MIPS_CONFIG0_K0_MASK 0x00000007 /* kseg0 coherency mode */
+
+#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
+#define MIPS_CONFIG1_TLBSZ_SHIFT 25
+#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
+#define MIPS_CONFIG1_IS_SHIFT 22
+#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
+#define MIPS_CONFIG1_IL_SHIFT 19
+#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
+#define MIPS_CONFIG1_IA_SHIFT 16
+#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
+#define MIPS_CONFIG1_DS_SHIFT 13
+#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
+#define MIPS_CONFIG1_DL_SHIFT 10
+#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
+#define MIPS_CONFIG1_DA_SHIFT 7
+#define MIPS_CONFIG1_LOWBITS 0x0000007F
+#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
+#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
+#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
+#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
+#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
+#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
+#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
+
/*
* Values for the code field in a break instruction.
*/
@@ -599,12 +391,6 @@
/*
* The low part of the TLB entry.
*/
-#define MIPS1_TLB_PFN 0xfffff000
-#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
-#define MIPS1_TLB_DIRTY_BIT 0x00000400
-#define MIPS1_TLB_VALID_BIT 0x00000200
-#define MIPS1_TLB_GLOBAL_BIT 0x00000100
-
#define MIPS3_TLB_PFN 0x3fffffc0
#define MIPS3_TLB_ATTR_MASK 0x00000038
#define MIPS3_TLB_ATTR_SHIFT 3
@@ -612,11 +398,8 @@
#define MIPS3_TLB_VALID_BIT 0x00000002
#define MIPS3_TLB_GLOBAL_BIT 0x00000001
-#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
-#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
-#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
/*
@@ -643,54 +426,32 @@
/*
* The high part of the TLB entry.
*/
-#define MIPS1_TLB_VPN 0xfffff000
-#define MIPS1_TLB_PID 0x00000fc0
-#define MIPS1_TLB_PID_SHIFT 6
-
#define MIPS3_TLB_VPN2 0xffffe000
#define MIPS3_TLB_ASID 0x000000ff
-#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
#define MIPS3_TLB_PID MIPS3_TLB_ASID
#define MIPS_TLB_VIRT_PAGE_SHIFT 12
/*
- * r3000: shift count to put the index in the right spot.
- */
-#define MIPS1_TLB_INDEX_SHIFT 8
-
-/*
* The first TLB that write random hits.
*/
-#define MIPS1_TLB_FIRST_RAND_ENTRY 8
#define MIPS3_TLB_WIRED_UPAGES 1
/*
* The number of process id entries.
*/
-#define MIPS1_TLB_NUM_PIDS 64
#define MIPS3_TLB_NUM_ASIDS 256
/*
* Patch codes to hide CPU design differences between MIPS1 and MIPS3.
*/
-
-/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
-
-#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
- && defined(MIPS1) /* XXX simonb must be neater! */
-#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
-#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
-#endif
-
#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
&& !defined(MIPS1) /* XXX simonb must be neater! */
#define MIPS_TLB_PID_SHIFT 0
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
#endif
-
#if !defined(MIPS_TLB_PID_SHIFT)
#define MIPS_TLB_PID_SHIFT \
((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
@@ -735,29 +496,15 @@
#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
/*
- * CPU revision IDs for some prehistoric processors.
+ * CPU revision IDs.
*/
-/* For MIPS_R3000 */
-#define MIPS_REV_R3000 0x20
-#define MIPS_REV_R3000A 0x30
-
-/* For MIPS_TX3900 */
-#define MIPS_REV_TX3912 0x10
-#define MIPS_REV_TX3922 0x30
-#define MIPS_REV_TX3927 0x40
-
/* For MIPS_R4000 */
-#define MIPS_REV_R4000_A 0x00
-#define MIPS_REV_R4000_B 0x22
#define MIPS_REV_R4000_C 0x30
#define MIPS_REV_R4400_A 0x40
#define MIPS_REV_R4400_B 0x50
#define MIPS_REV_R4400_C 0x60
-/* For MIPS_TX4900 */
-#define MIPS_REV_TX4927 0x22
-
/*
* CPU processor revision IDs for company ID == 1 (MIPS)
*/
@@ -776,12 +523,14 @@
#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
/*
- * Alchemy (company ID 3) use the processor ID field to donote the CPU core
+ * AMD (company ID 3) use the processor ID field to donote the CPU core
* revision and the company options field do donate the SOC chip type.
*/
+
/* CPU processor revision IDs */
#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
+
/* CPU company options IDs */
#define MIPS_AU1000 0x00
#define MIPS_AU1500 0x01
@@ -789,7 +538,7 @@
#define MIPS_AU1550 0x03
/*
- * CPU processor revision IDs for company ID == 4 (SiByte)
+ * CPU processor revision IDs for company ID == 4 (Broadcom)
*/
#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
@@ -810,14 +559,4 @@
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
-#ifdef ENABLE_MIPS_TX3900
-#include <mips/r3900regs.h>
-#endif
-#ifdef MIPS3_5900
-#include <mips/r5900regs.h>
-#endif
-#ifdef MIPS64_SB1
-#include <mips/sb1regs.h>
-#endif
-
#endif /* _MIPS_CPUREGS_H_ */
==== //depot/projects/mips2/src/sys/mips/include/trap.h#3 (text+ko) ====
@@ -44,9 +44,13 @@
#define TrTr 13
#define TrVCEI 14
#define TrFPE 15
-/* 16 - 22 */
+/* 16 - 17 */
+#define TrC2E 18 /* MIPS64 */
+#define TrMDMX 22 /* MIPS64 */
#define TrWATCH 23
-/* 24 - 30 */
+#define TrMCE 24 /* MIPS64 */
+/* 25 - 29 */
+#define TrCacheErr 30 /* MIPS64 */
#define TrVCED 31
#ifndef LOCORE /* XXX */
==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#11 (text+ko) ====
@@ -25,13 +25,6 @@
* $FreeBSD$
*/
-/*
- * XXMIPS: __RMAN_RESOURCE_VISIBLE is no longer present in the tree, and for
- * struct resource we have nice interface.
- */
-#if 0
-#define __RMAN_RESOURCE_VISIBLE
-#endif
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/module.h>
@@ -46,11 +39,9 @@
#include <machine/cache.h>
#include <machine/cpufunc.h>
-/*
- * XXMIPS: I did intr.h -> intr_machdep.h conversion here.
- */
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
#include <machine/intr_machdep.h>
-
#include <machine/locore.h>
#include <machine/pte.h>
#include <machine/tlb.h>
@@ -59,14 +50,28 @@
* cpu_id and fpu_id are initialized in locore.S. mips_num_tlb_entries is
* initialized by us in the mips_cpu_init thingo.
*/
-int mips_num_tlb_entries, cpu_id, fpu_id;
+int mips_num_tlb_entries;
+int cpu_id;
+int fpu_id;
+
+void mips_get_identity(struct mips_cpuinfo *cpuinfo);
/*
- * XXMIPS: Check format strings.
- * Uncomment this one once VECI macro defined below is uncommented.
+ * Exception vector table management.
*/
+#define MIPS_DECLARE_VECTOR(class) \
+ extern char class ## Vector[], class ## VectorEnd[]
+#define MIPS_INSTALL_VECTOR(vector, class) \
+ mips_vector_do_install(MIPS_VEC_ ## vector, \
+ class ## Vector, \
+ class ## VectorEnd)
+
+MIPS_DECLARE_VECTOR(TLBMiss);
+MIPS_DECLARE_VECTOR(Cache);
+MIPS_DECLARE_VECTOR(Exception);
+
static void
-mips_vector_install(vm_offset_t addr, char *begin, char *end)
+mips_vector_do_install(vm_offset_t addr, char *begin, char *end)
{
size_t len, max;
@@ -82,156 +87,96 @@
memcpy((void *)addr, begin, len);
}
-/*
- * XXMIPS: Those declares external addresses of exception handlers to be used. Take a
- * look at support.S to see *Vector code.
- */
-#define VEC(class) extern char class ## Vector[], class ## VectorEnd[]
-
-/*
- * XXMIPS: This makes cooperation with exception handler more handy. Less hand-typing
- * is needed. Take a look at mips_vector_init() in this file to see a usage.
- */
-#define VECI(vec, class) mips_vector_install(vec ## _EXC_VEC, \
- class ## Vector, \
- class ## VectorEnd)
-/*
- * General exception handler.
- */
-VEC(Exception);
-
-/*
- * TLB miss, XTLB miss handler.
- */
-VEC(TLBMiss);
-VEC(XTLBMiss);
-
-/*
- * Cache error handler.
- */
-VEC(Cache);
-
-/*
- * Here you have for example: extern char CacheVector, CacheVestorEnd
- */
-
-/*
- * XXMIPS: error : large integer implicitly truncated to unsigned type. This
- * error will stay unless we define proper addresses of exception vectors in
- * cpufunc.h.
- */
static void
mips_vector_init(void)
{
- VECI(MIPS_UTLB_MISS, TLBMiss);
- VECI(MIPS3_XTLB_MISS, TLBMiss);
- VECI(MIPS3_CACHE_ERR, Cache);
- VECI(MIPS3_GEN, Exception);
-
+ MIPS_INSTALL_VECTOR(TLB, TLBMiss);
+ MIPS_INSTALL_VECTOR(CACHE, Cache);
+ MIPS_INSTALL_VECTOR(INTERRUPT, Exception); /* XXX */
+ MIPS_INSTALL_VECTOR(GENERIC, Exception);
+
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
+#undef MIPS_INSTALL_VECTOR
+#undef MIPS_DECLARE_VECTOR
+
/*
- * Identify a CPU enough to tell sweet lies about it. We only identify CPUs
- * we know we support here, and later.
+ * Attempt to identify the MIPS CPU as much as possible.
*
- * This is the WHICH TYPE FINDER. It finds which type of CPU it is :)
+ * XXX: Assumes the CPU is MIPS32 compliant.
+ * XXX: For now, skip config register selections 2 and 3
+ * as we don't currently use L2/L3 cache or additional
+ * MIPS32 processor features.
*/
-struct wtf {
- unsigned long wtf_class;
- const char *wtf_type;
- unsigned long wtf_ntlbs;
- const char *wtf_fpu;
-};
+void
+mips_get_identity(struct mips_cpuinfo *cpuinfo)
+{
+ u_int32_t prid;
+ u_int32_t cfg0;
+ u_int32_t cfg1;
+ u_int32_t tmp;
+
+ memset(cpuinfo, 0, sizeof(struct mips_cpuinfo));
+
+ /* Read and store the PrID ID for CPU identification. */
+ prid = mips_rd_prid();
+ cpuinfo->cpu_vendor = MIPS_PRID_CID(prid);
+ cpuinfo->cpu_rev = MIPS_PRID_REV(prid);
+ cpuinfo->cpu_impl = MIPS_PRID_IMPL(prid);
-static void
-mips_wtf(struct wtf *wtf)
-{
+ /* Read config register selection 0 to learn TLB type. */
+ cfg0 = mips_rd_config();
- /*
- * XXXMIPS: Comment it for now, since I haven't get to
- * CPU-specifications and differences between them. Bring sample
- * values here.
- */
- wtf->wtf_class = MIPS_R4000;
- wtf->wtf_type = "XZ";
- wtf->wtf_ntlbs = 16; /* XX Find the right value. */
- wtf->wtf_fpu = "YC";
-#if 0
- unsigned long cpu_class;
- const char *cpu_type;
- unsigned long cpu_ntlbs;
- const char *cpu_fpu;
+ cpuinfo->tlb_type = ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT);
- switch (MIPS_PRID_IMPL(cpu_id)) {
- case MIPS_R4000:
- cpu_class = MIPS_R4000;
- switch (MIPS_PRID_REV(cpu_id)) {
- case MIPS_REV_R4400_A:
- case MIPS_REV_R4400_B:
- case MIPS_REV_R4400_C:
- cpu_type = "MIPS R4400";
- cpu_ntlbs = 48;
- break;
- default:
- goto unknown;
- }
- break;
- default:
- goto unknown;
- }
- switch (MIPS_PRID_IMPL(fpu_id)) {
- case MIPS_R4010:
- cpu_fpu = "MIPS R4010 FPC";
- break;
- default:
- goto unknown;
- }
- wtf->wtf_class = cpu_class;
- wtf->wtf_type = cpu_type;
- wtf->wtf_ntlbs = cpu_ntlbs;
- wtf->wtf_fpu = cpu_fpu;
+ /* If config register selection 1 does not exist, exit. */
+ if (!(cfg0 & MIPS_CONFIG_CM))
return;
-unknown:
- printf("Unknown CPU cpu_id=%x\n", cpu_id);
- printf("Unknown FPU fpu_id=%x\n", fpu_id);
- panic("Please send this output to freebsd-mips at freeebsd.org");
-#endif
+
+ /* Learn TLB size and L1 cache geometry. */
+ cfg1 = mips_rd_config_sel1();
+ cpuinfo->tlb_nentries = ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
+
+ /* L1 instruction cache. */
+ tmp = 1 << (((cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT) + 1);
+ if (tmp != 0) {
+ cpuinfo->l1.ic_linesize = tmp;
+ cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1;
+ cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
+ }
+
+ /* L1 data cache. */
+ tmp = 1 << (((cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT) + 1);
+ if (tmp != 0) {
+ cpuinfo->l1.dc_linesize = tmp;
+ cpuinfo->l1.dc_nways = (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1;
+ cpuinfo->l1.dc_nsets = 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6);
+ }
}
-/*
- * Possible code path
- * ------------------
- * mips_init(): (from machdep.c)
- * |
- * +- mips_cpu_init(): (this file -- cpu.c)
- * |
- * +- mips_wtf() (this file -- cpu.c) ok
- * +- mips_config_cache() (this file -- cpu.c) stub
- * +- tlb_invalidate_all() (tlb.c)
- * +- mips_vector_init() (this file -- cpu.c)
- * +- mips_icache_sync_all() (cache.c ?) XX
- * +- mips_dcache_wbinv_all() (cache.c ?) XX
- */
void
mips_cpu_init(void)
{
- struct wtf wtf;
+ struct mips_cpuinfo cpuinfo;
- /* XXX PCPU */
- mips_wtf(&wtf);
+ mips_get_identity(&cpuinfo);
+ mips_num_tlb_entries = cpuinfo.tlb_nentries;
- mips_num_tlb_entries = wtf.wtf_ntlbs;
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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