PERFORCE change 101556 for review

[Bruce M Simpson]

http://perforce.freebsd.org/chv.cgi?CH=101556

Change 101556 by bms at bms_montagne on 2006/07/14 15:13:50

	Fold 64-bit stuff under #ifdef MIPS64.
	Cut down comments

Affected files ...

.. //depot/projects/mips2/src/sys/mips/mips/tlb.c#5 edit

Differences ...

==== //depot/projects/mips2/src/sys/mips/mips/tlb.c#5 (text+ko) ====

@@ -107,22 +107,19 @@
 	 * Initialise ASID and clear TLB and set up for 4K pages.
 	 */
 	mips_wr_entryhi(0);
+	mips_wr_pagemask(0); /* XXX 4K */
 	tlb_invalidate_all();
-	mips_wr_pagemask(0); /* XXX 4K */
 
 	/*
 	 * Just one wired TLB entry.
 	 */
 	mips_wr_wired(1);
 
-	/*
-	 * XXXMIPS: Does xcontext exist on mips32?
-	 */
-#if 0
+#ifdef CPU_MIPS64
 	/*
 	 * Set up page table.
 	 */
-	mips_wr_xcontext((uintptr_t)kptmap); /* XXX: mips64 */
+	mips_wr_xcontext((uintptr_t)kptmap);
 #endif
 }
 
@@ -175,9 +172,6 @@
 	tlb_remove_pages(pmap, va, eva - va);
 }
 
-/*
- * XXXMIPS: Check this one.
- */
 void
 tlb_update(vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1)
 {
@@ -185,11 +179,7 @@
 	int i;
 
 	va &= ~PAGE_MASK;
-	/*
-	 * XXXMIPS: This will probably mean bringing stuff from NetBSD, as
-	 * juli's code has offsets and sizes for mips64.
-	 */
-#if 0
+#ifdef CPU_MIPS64
 	ehi = MIPS_HI_ENTRY(va, /*asid*/0);
 #endif
 	ehi = 0;
@@ -225,9 +215,9 @@
 	/* Bogus VPN2. */
 	ehi = MIPS_KSEG1_END + 2 * i * PAGE_SIZE;
 	mips_wr_index(i);
-#if 0
+#ifdef CPU_MIPS64
 	mips_wr_entrylo0(0);
-	mips_wr_entrylo1(0);		/* XXX mips64 */
+	mips_wr_entrylo1(0);
 #else
 	mips_wr_entrylow(0);
 #endif
@@ -235,9 +225,6 @@
 	mips_tlbwi();
 }
 
-/*
- * XXXMIPS: Check this one.
- */
 void
 tlb_invalidate_page(vm_offset_t va)
 {
@@ -245,11 +232,7 @@
 	int i;
 
 	va &= ~PAGE_MASK;
-	/*
-	 * XXXMIPS: This will probably mean bringing stuff from NetBSD, as
-	 * juli's code has offsets and sizes for mips64.
-	 */
-#if 0
+#ifdef CPU_MIPS64
 	ehi = MIPS_HI_ENTRY(va, /*asid*/0);
 #endif
 	ehi = 0;