PERFORCE change 101169 for review
Wojciech A. Koszek
wkoszek at FreeBSD.org
Sun Jul 9 21:56:20 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=101169
Change 101169 by wkoszek at wkoszek_laptop on 2006/07/09 21:55:17
Bring cpuregs.h from NetBSD. cognet@ mentioned about specialreg.h,
but I'm not happy with it for now. I have small plan regarding
header files for MIPS, but will discuss it later.
Makefile.mips:
- experimentally bring -D_LOCORE and -DLOCORE.
cpufunc.h:
- MIPS_SR_IE -> MIPS_SR_INT_IE due to the name change, which is
caused by bringing 32 bit register specifications from NetBSD to
cpuregs.h
cpu.c:
- enable mips_vector_install() and mips_vector_init().
Tree is unbuildable at this stage due to a problem with macros
names, which concatated should give you valid function name.
Alex agreed to work on this.
Affected files ...
.. //depot/projects/mips2/src/sys/conf/Makefile.mips#6 edit
.. //depot/projects/mips2/src/sys/mips/include/cpufunc.h#13 edit
.. //depot/projects/mips2/src/sys/mips/include/cpuregs.h#2 edit
.. //depot/projects/mips2/src/sys/mips/mips/cpu.c#6 edit
Differences ...
==== //depot/projects/mips2/src/sys/conf/Makefile.mips#6 (text+ko) ====
@@ -40,6 +40,7 @@
CFLAGS+=-fno-pic $(ARCH_FLAGS)
SYSTEM_LD+= -Ttext 0x80100000
HACK_EXTRA_FLAGS+=-fno-pic $(ARCH_FLAGS)
+ASM_FLAGS+=${CFLAGS} -D_LOCORE -DLOCORE
.if defined(MIPS_LITTLE_ENDIAN)
CFLAGS+=-EL
==== //depot/projects/mips2/src/sys/mips/include/cpufunc.h#13 (text+ko) ====
@@ -186,7 +186,7 @@
register_t s;
s = mips_rd_status();
- mips_wr_status(s & ~MIPS_SR_IE);
+ mips_wr_status(s & ~MIPS_SR_INT_IE);
return (s);
}
@@ -197,7 +197,7 @@
register_t s;
s = mips_rd_status();
- mips_wr_status(s | MIPS_SR_IE);
+ mips_wr_status(s | MIPS_SR_INT_IE);
return (s);
}
==== //depot/projects/mips2/src/sys/mips/include/cpuregs.h#2 (text+ko) ====
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.55 2002/07/26 00:43:54 simonb Exp $ */
+/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -15,11 +15,7 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
+ * 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
@@ -61,6 +57,11 @@
#define _MIPS_CPUREGS_H_
#include <sys/cdefs.h> /* For __CONCAT() */
+
+#if defined(_KERNEL_OPT)
+#include "opt_cputype.h"
+#endif
+
/*
* Address space.
* 32-bit mips CPUS partition their 32-bit address space into four segments:
@@ -77,36 +78,29 @@
#define MIPS_KUSEG_START 0x0
#define MIPS_KSEG0_START 0x80000000
-#define MIPS_KSEG0_END 0x9fffffff
#define MIPS_KSEG1_START 0xa0000000
-#define MIPS_KSEG1_END 0xbfffffff
#define MIPS_KSEG2_START 0xc0000000
#define MIPS_MAX_MEM_ADDR 0xbe000000
#define MIPS_RESERVED_ADDR 0xbfc80000
#define MIPS_PHYS_MASK 0x1fffffff
-#define MIPS_KSEG0_TO_PHYS(x) ((vm_offset_t)(x) & MIPS_PHYS_MASK)
-#define MIPS_PHYS_TO_KSEG0(x) ((vm_offset_t)(x) | MIPS_KSEG0_START)
-#define MIPS_KSEG1_TO_PHYS(x) ((vm_offset_t)(x) & MIPS_PHYS_MASK)
-#define MIPS_PHYS_TO_KSEG1(x) ((vm_offset_t)(x) | MIPS_KSEG1_START)
+#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
+#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
+#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
+#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
+
+/* Map virtual address to index in mips3 r4k virtually-indexed cache */
+#define MIPS3_VA_TO_CINDEX(x) \
+ ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
- /* Uncached */
-#define MIPS_XKPHYS_UC (2)
- /* Cacheable noncoherent */
-#define MIPS_XKPHYS_CNC (3)
- /* Cacheable coherent exclusive */
-#define MIPS_XKPHYS_CCE (4)
- /* Cacheable coherent exclusive on write */
-#define MIPS_XKPHYS_CCEW (5)
- /* Cacheable coherent update on write */
-#define MIPS_XKPHYS_CCUW (6)
/* CPU dependent mtc0 hazard hook */
-#define COP0_SYNC /* nothing */
+#define COP0_SYNC /* nothing */
+#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
/*
* The bits in the cause register.
@@ -124,7 +118,8 @@
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
-#define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
+#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
+#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
@@ -156,7 +151,10 @@
/* r4k and r3k differences, see below */
-#define MIPS_SR_INT_IE MIPS_SR_IE
+#define MIPS_SR_INT_IE 0x00000001
+/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
+/*#define MIPS_SR_INT_MASK 0x0000ff00*/
+
/*
* The R2000/R3000-specific status register bit definitions.
@@ -175,33 +173,78 @@
* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
*/
+#define MIPS1_PARITY_ERR 0x00100000
+#define MIPS1_CACHE_MISS 0x00080000
+#define MIPS1_PARITY_ZERO 0x00040000
+#define MIPS1_SWAP_CACHES 0x00020000
+#define MIPS1_ISOL_CACHES 0x00010000
+
+#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
+#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
+#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
+
+/* backwards compatibility */
+#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
+#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
+#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
+#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
+#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
+
+#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
+#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
+#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
+#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
+#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
+
/*
* R4000 status register bit definitons,
* where different from r2000/r3000.
*/
-#define MIPS_SR_XX 0x80000000
-#define MIPS_SR_RP 0x08000000
-#define MIPS_SR_FR_32 0x04000000
-#define MIPS_SR_RE 0x02000000
+#define MIPS3_SR_XX 0x80000000
+#define MIPS3_SR_RP 0x08000000
+#define MIPS3_SR_FR 0x04000000
+#define MIPS3_SR_RE 0x02000000
+
+#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
+#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
+#define MIPS3_SR_SR 0x00100000
+#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
+#define MIPS3_SR_DIAG_CH 0x00040000
+#define MIPS3_SR_DIAG_CE 0x00020000
+#define MIPS3_SR_DIAG_PE 0x00010000
+#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
+#define MIPS3_SR_KX 0x00000080
+#define MIPS3_SR_SX 0x00000040
+#define MIPS3_SR_UX 0x00000020
+#define MIPS3_SR_KSU_MASK 0x00000018
+#define MIPS3_SR_KSU_USER 0x00000010
+#define MIPS3_SR_KSU_SUPER 0x00000008
+#define MIPS3_SR_KSU_KERNEL 0x00000000
+#define MIPS3_SR_ERL 0x00000004
+#define MIPS3_SR_EXL 0x00000002
+
+#ifdef MIPS3_5900
+#undef MIPS_SR_INT_IE
+#define MIPS_SR_INT_IE 0x00010001 /* XXX */
+#endif
+
+#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
+#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
+#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
+#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
+#define MIPS_SR_KX MIPS3_SR_KX
+#define MIPS_SR_SX MIPS3_SR_SX
+#define MIPS_SR_UX MIPS3_SR_UX
+
+#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
+#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
+#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
+#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
+#define MIPS_SR_ERL MIPS3_SR_ERL
+#define MIPS_SR_EXL MIPS3_SR_EXL
-#define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
-#define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
-#define MIPS_SR_SR 0x00100000
-#define MIPS_SR_EIE 0x00100000 /* TX79/R5900 */
-#define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
-#define MIPS_SR_DIAG_CH 0x00040000
-#define MIPS_SR_DIAG_CE 0x00020000
-#define MIPS_SR_DIAG_PE 0x00010000
-#define MIPS_SR_KX 0x00000080
-#define MIPS_SR_SX 0x00000040
-#define MIPS_SR_UX 0x00000020
-#define MIPS_SR_KSU_MASK 0x00000018
-#define MIPS_SR_KSU_USER 0x00000010
-#define MIPS_SR_KSU_SUPER 0x00000008
-#define MIPS_SR_KSU_KERNEL 0x00000000
-#define MIPS_SR_ERL 0x00000004
-#define MIPS_SR_EXL 0x00000002
-#define MIPS_SR_IE 0x00000001
/*
* The interrupt masks.
@@ -219,13 +262,25 @@
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
+ * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
+ * choose to enable this interrupt.
+ */
+#if defined(MIPS3_ENABLE_CLOCK_INTR)
+#define MIPS3_INT_MASK MIPS_INT_MASK
+#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
+#else
+#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
+#endif
+
+/*
* The bits in the context register.
- *
- * XXX XContext
*/
+#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
+#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
-#define MIPS_CNTXT_PTE_BASE 0xFF800000
-#define MIPS_CNTXT_BAD_VPN2 0x007FFFF0
+#define MIPS3_CNTXT_PTE_BASE 0xFF800000
+#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
/*
* The bits in the MIPS3 config register.
@@ -233,93 +288,137 @@
* bit 0..5: R/W, Bit 6..31: R/O
*/
-/* kseg0 coherency algorithm - see MIPS_TLB_ATTR values */
-#define MIPS_CONFIG_K0_MASK 0x00000007
+/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+#define MIPS3_CONFIG_K0_MASK 0x00000007
/*
* R/W Update on Store Conditional
* 0: Store Conditional uses coherency algorithm specified by TLB
* 1: Store Conditional uses cacheable coherent update on write
*/
-#define MIPS_CONFIG_CU 0x00000008
+#define MIPS3_CONFIG_CU 0x00000008
-#define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
-#define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
-#define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
+#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
+#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
+#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
(((config) & (bit)) ? 32 : 16)
-#define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
-#define MIPS_CONFIG_DC_SHIFT 6
-#define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
-#define MIPS_CONFIG_IC_SHIFT 9
-#define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
-#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
+#define MIPS3_CONFIG_DC_SHIFT 6
+#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
+#define MIPS3_CONFIG_IC_SHIFT 9
+#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
+
+/* Cache size mode indication: available only on Vr41xx CPUs */
+#define MIPS3_CONFIG_CS 0x00001000
+#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
+#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
((base) << (((config) & (mask)) >> (shift)))
/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
-#define MIPS_CONFIG_SE 0x00001000
+#define MIPS3_CONFIG_SE 0x00001000
/* Block ordering: 0: sequential, 1: sub-block */
-#define MIPS_CONFIG_EB 0x00002000
+#define MIPS3_CONFIG_EB 0x00002000
/* ECC mode - 0: ECC mode, 1: parity mode */
-#define MIPS_CONFIG_EM 0x00004000
+#define MIPS3_CONFIG_EM 0x00004000
/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
-#define MIPS_CONFIG_BE 0x00008000
+#define MIPS3_CONFIG_BE 0x00008000
/* Dirty Shared coherency state - 0: enabled, 1: disabled */
-#define MIPS_CONFIG_SM 0x00010000
+#define MIPS3_CONFIG_SM 0x00010000
/* Secondary Cache - 0: present, 1: not present */
-#define MIPS_CONFIG_SC 0x00020000
+#define MIPS3_CONFIG_SC 0x00020000
/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
-#define MIPS_CONFIG_EW_MASK 0x000c0000
-#define MIPS_CONFIG_EW_SHIFT 18
+#define MIPS3_CONFIG_EW_MASK 0x000c0000
+#define MIPS3_CONFIG_EW_SHIFT 18
/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
-#define MIPS_CONFIG_SW 0x00100000
+#define MIPS3_CONFIG_SW 0x00100000
/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
-#define MIPS_CONFIG_SS 0x00200000
+#define MIPS3_CONFIG_SS 0x00200000
/* Secondary Cache line size */
-#define MIPS_CONFIG_SB_MASK 0x00c00000
-#define MIPS_CONFIG_SB_SHIFT 22
-#define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
- (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
+#define MIPS3_CONFIG_SB_MASK 0x00c00000
+#define MIPS3_CONFIG_SB_SHIFT 22
+#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
+ (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
/* Write back data rate */
-#define MIPS_CONFIG_EP_MASK 0x0f000000
-#define MIPS_CONFIG_EP_SHIFT 24
+#define MIPS3_CONFIG_EP_MASK 0x0f000000
+#define MIPS3_CONFIG_EP_SHIFT 24
/* System clock ratio - this value is CPU dependent */
-#define MIPS_CONFIG_EC_MASK 0x70000000
-#define MIPS_CONFIG_EC_SHIFT 28
+#define MIPS3_CONFIG_EC_MASK 0x70000000
+#define MIPS3_CONFIG_EC_SHIFT 28
/* Master-Checker Mode - 1: enabled */
-#define MIPS_CONFIG_CM 0x80000000
+#define MIPS3_CONFIG_CM 0x80000000
+
+/*
+ * The bits in the MIPS4 config register.
+ */
+
+/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
+#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
+#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
+#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
+#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
+#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
+#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
+#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
+#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
+#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
+#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
+#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
+#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
+#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
+
+#define MIPS4_CONFIG_DC_SHIFT 26
+#define MIPS4_CONFIG_IC_SHIFT 29
+
+#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+ ((base) << (((config) & (mask)) >> (shift)))
+
+#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
+ (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
/*
* Location of exception vectors.
*
* Common vectors: reset and UTLB miss.
*/
-#define MIPS_RESET_EXC_VEC 0xFFFFFFFFBFC00000
-#define MIPS_UTLB_MISS_EXC_VEC 0xFFFFFFFF80000000
+#define MIPS_RESET_EXC_VEC 0xBFC00000
+#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
+
+/*
+ * MIPS-1 general exception vector (everything else)
+ */
+#define MIPS1_GEN_EXC_VEC 0x80000080
/*
* MIPS-III exception vectors
*/
-#define MIPS_XTLB_MISS_EXC_VEC 0xFFFFFFFF80000080
-#define MIPS_CACHE_ERR_EXC_VEC 0xFFFFFFFF80000100
-#define MIPS_GEN_EXC_VEC 0xFFFFFFFF80000180
+#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
+#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
+#define MIPS3_GEN_EXC_VEC 0x80000180
+
+/*
+ * TX79 (R5900) exception vectors
+ */
+#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
+#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
/*
* MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
*/
-#define MIPS_INTR_EXC_VEC 0xFFFFFFFF80000200
+#define MIPS3_INTR_EXC_VEC 0x80000200
/*
* Coprocessor 0 registers:
@@ -366,11 +465,17 @@
* 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
* 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
*/
-#ifdef LOCORE
+
+/*
+ * XXMIPS: Does LOCORE defines buy us something? Check which one is it.
+ */
+#if defined(_LOCORE) || defined(LOCORE)
#define _(n) $n
#else
#define _(n) n
#endif
+
+
#define MIPS_COP_0_TLB_INDEX _(0)
#define MIPS_COP_0_TLB_RANDOM _(1)
/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
@@ -379,8 +484,6 @@
/* $5 and $6 new with MIPS-III */
#define MIPS_COP_0_BAD_VADDR _(8)
#define MIPS_COP_0_TLB_HI _(10)
-#define MIPS_COP_0_STATUS_REG _(12)
-#define MIPS_COP_0_CAUSE_REG _(13)
#define MIPS_COP_0_STATUS _(12)
#define MIPS_COP_0_CAUSE _(13)
#define MIPS_COP_0_EXC_PC _(14)
@@ -443,13 +546,13 @@
*/
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
-#define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
+#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
/*
* The floating point version and status registers.
*/
-#define MIPS_FPU_ID _(0)
-#define MIPS_FPU_CSR _(31)
+#define MIPS_FPU_ID $0
+#define MIPS_FPU_CSR $31
/*
* The floating point coprocessor status register bits.
@@ -480,7 +583,8 @@
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
#define MIPS_FPU_COND_BIT 0x00800000
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
-#define MIPS_FPC_MBZ_BITS 0xfe7c0000
+#define MIPS1_FPC_MBZ_BITS 0xff7c0000
+#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
/*
@@ -489,11 +593,109 @@
#define MIPS_OPCODE_SHIFT 26
#define MIPS_OPCODE_C1 0x11
+
/*
+ * The low part of the TLB entry.
+ */
+#define MIPS1_TLB_PFN 0xfffff000
+#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
+#define MIPS1_TLB_DIRTY_BIT 0x00000400
+#define MIPS1_TLB_VALID_BIT 0x00000200
+#define MIPS1_TLB_GLOBAL_BIT 0x00000100
+
+#define MIPS3_TLB_PFN 0x3fffffc0
+#define MIPS3_TLB_ATTR_MASK 0x00000038
+#define MIPS3_TLB_ATTR_SHIFT 3
+#define MIPS3_TLB_DIRTY_BIT 0x00000004
+#define MIPS3_TLB_VALID_BIT 0x00000002
+#define MIPS3_TLB_GLOBAL_BIT 0x00000001
+
+#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
+#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
+#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
+#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
+#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
+#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
+
+/*
+ * MIPS3_TLB_ATTR values - coherency algorithm:
+ * 0: cacheable, noncoherent, write-through, no write allocate
+ * 1: cacheable, noncoherent, write-through, write allocate
+ * 2: uncached
+ * 3: cacheable, noncoherent, write-back (noncoherent)
+ * 4: cacheable, coherent, write-back, exclusive (exclusive)
+ * 5: cacheable, coherent, write-back, exclusive on write (sharable)
+ * 6: cacheable, coherent, write-back, update on write (update)
+ * 7: uncached, accelerated (gather STORE operations)
+ */
+#define MIPS3_TLB_ATTR_WT 0 /* IDT */
+#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
+#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
+#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
+#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
+#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
+#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
+#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
+
+
+/*
+ * The high part of the TLB entry.
+ */
+#define MIPS1_TLB_VPN 0xfffff000
+#define MIPS1_TLB_PID 0x00000fc0
+#define MIPS1_TLB_PID_SHIFT 6
+
+#define MIPS3_TLB_VPN2 0xffffe000
+#define MIPS3_TLB_ASID 0x000000ff
+
+#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
+#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
+#define MIPS3_TLB_PID MIPS3_TLB_ASID
+#define MIPS_TLB_VIRT_PAGE_SHIFT 12
+
+/*
+ * r3000: shift count to put the index in the right spot.
+ */
+#define MIPS1_TLB_INDEX_SHIFT 8
+
+/*
+ * The first TLB that write random hits.
+ */
+#define MIPS1_TLB_FIRST_RAND_ENTRY 8
+#define MIPS3_TLB_WIRED_UPAGES 1
+
+/*
* The number of process id entries.
*/
-#define MIPS_TLB_NUM_ASIDS 256
+#define MIPS1_TLB_NUM_PIDS 64
+#define MIPS3_TLB_NUM_ASIDS 256
+
+/*
+ * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
+ */
+
+/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
+
+#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
+ && defined(MIPS1) /* XXX simonb must be neater! */
+#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
+#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
+#endif
+
+#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
+ && !defined(MIPS1) /* XXX simonb must be neater! */
#define MIPS_TLB_PID_SHIFT 0
+#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
+#endif
+
+
+#if !defined(MIPS_TLB_PID_SHIFT)
+#define MIPS_TLB_PID_SHIFT \
+ ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
+
+#define MIPS_TLB_NUM_PIDS \
+ ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
+#endif
/*
* CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
@@ -526,7 +728,9 @@
#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
+#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
+#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
/*
* CPU revision IDs for some prehistoric processors.
@@ -543,7 +747,8 @@
/* For MIPS_R4000 */
#define MIPS_REV_R4000_A 0x00
-#define MIPS_REV_R4000_B 0x30
+#define MIPS_REV_R4000_B 0x22
+#define MIPS_REV_R4000_C 0x30
#define MIPS_REV_R4400_A 0x40
#define MIPS_REV_R4400_B 0x50
#define MIPS_REV_R4400_C 0x60
@@ -557,8 +762,16 @@
#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
+#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
+#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
+#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
+#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
+#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
+#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
+#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
+#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
/*
* Alchemy (company ID 3) use the processor ID field to donote the CPU core
@@ -571,6 +784,7 @@
#define MIPS_AU1000 0x00
#define MIPS_AU1500 0x01
#define MIPS_AU1100 0x02
+#define MIPS_AU1550 0x03
/*
* CPU processor revision IDs for company ID == 4 (SiByte)
@@ -594,4 +808,14 @@
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
+#ifdef ENABLE_MIPS_TX3900
+#include <mips/r3900regs.h>
+#endif
+#ifdef MIPS3_5900
+#include <mips/r5900regs.h>
+#endif
+#ifdef MIPS64_SB1
+#include <mips/sb1regs.h>
+#endif
+
#endif /* _MIPS_CPUREGS_H_ */
==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#6 (text+ko) ====
@@ -65,7 +65,6 @@
* XXMIPS: Check format strings.
* Uncomment this one once VECI macro defined below is uncommented.
*/
-#if 0
static void
mips_vector_install(vm_offset_t addr, char *begin, char *end)
{
@@ -82,7 +81,6 @@
(intmax_t) addr);
memcpy((void *)addr, begin, len);
}
-#endif
/*
* XXMIPS: Those declares external addresses of exception handlers to be used. Take a
@@ -125,12 +123,12 @@
static void
mips_vector_init(void)
{
-#if 0
+
VECI(UTLB_MISS, TLBMiss);
VECI(XTLB_MISS, XTLBMiss);
VECI(CACHE_ERR, Cache);
VECI(GEN, Exception);
-#endif
+
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
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