PERFORCE change 101039 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=101039

Change 101039 by imp at imp_lighthouse on 2006/07/08 17:27:49

	start to implement transfer.  I gotta setup the busdma stuff
	before I can finish.

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_spi.c#5 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_spireg.h#5 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_spi.c#5 (text+ko) ====

@@ -51,13 +51,6 @@
 	struct resource *irq_res;	/* IRQ resource */
 	struct resource	*mem_res;	/* Memory resource */
 	struct mtx sc_mtx;		/* basically a perimeter lock */
-	int flags;
-#define XFER_PENDING	1		/* true when transfer taking place */
-#define OPENED		2		/* Device opened */
-#define RXRDY		4
-#define TXCOMP		8
-#define TXRDY		0x10
-	struct cdev *cdev;
 };
 
 static inline uint32_t
@@ -198,7 +191,28 @@
 static int
 at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
 {
-	return EIO;
+	struct at91_spi_softc *sc;
+
+	sc = device_get_softc(dev);
+	WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
+#if 0
+	// XXX setup busdma
+	pSPI->SPI_RPR = (unsigned)pCommand->rx_cmd;
+	pSPI->SPI_RCR = pCommand->rx_cmd_size;
+	pSPI->SPI_TPR = (unsigned)pCommand->tx_cmd;
+	pSPI->SPI_TCR = pCommand->tx_cmd_size;
+
+	pSPI->SPI_TNPR = (unsigned)pCommand->tx_data;
+	pSPI->SPI_TNCR = pCommand->tx_data_size;
+	pSPI->SPI_RNPR = (unsigned)pCommand->rx_data;
+	pSPI->SPI_RNCR = pCommand->rx_data_size;
+#endif
+	WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);
+
+	// wait for completion
+	while (RD4(sc, SPI_SR) & SPI_SR_ENDRX)
+		DELAY(700);
+	return (0);
 }
 
 static device_method_t at91_spi_methods[] = {

==== //depot/projects/arm/src/sys/arm/at91/at91_spireg.h#5 (text+ko) ====

@@ -33,10 +33,27 @@
 #define	  SPI_CR_SWRST		0x8
 #define SPI_MR		0x04		/* MR: Mode Register */
 #define	  SPI_MR_MSTR		0x01
+#define	  SPI_MR_PS		0x02
+#define   SPI_MR_PCSDEC		0x04
+#define   SPI_MR_DIV32		0x08
 #define	  SPI_MR_MODFDIS	0x10
+#define   SPI_MR_LLB		0x80
+#define   SPI_MR_PSC_CS0	0xe0000
+#define   SPI_MR_PSC_CS1	0xd0000
+#define	  SPI_MR_PSC_CS2	0xb0000
+#define	  SPI_MR_PSC_CS3	0x70000
 #define SPI_RDR		0x08		/* RDR: Receive Data Register */
 #define SPI_TDR		0x0c		/* TDR: Transmit Data Register */
 #define SPI_SR		0x10		/* SR: Status Register */
+#define	  SPI_SR_RDRF		0x00001
+#define	  SPI_SR_TDRE		0x00002
+#define	  SPI_SR_MODF		0x00004
+#define	  SPI_SR_OVRES		0x00008
+#define	  SPI_SR_ENDRX		0x00010
+#define	  SPI_SR_ENDTX		0x00020
+#define	  SPI_SR_RXBUFE		0x00040
+#define	  SPI_SR_TXBUFE		0x00080
+#define	  SPI_SR_SPIENS		0x10000
 #define	SPI_IER		0x14		/* IER: Interrupt Enable Regsiter */
 #define	SPI_IDR		0x18		/* IDR: Interrupt Disable Regsiter */
 #define	SPI_IMR		0x1c		/* IMR: Interrupt Mask Regsiter */