PERFORCE change 65299 for review
Marcel Moolenaar
marcel at FreeBSD.org
Tue Nov 16 22:54:05 PST 2004
http://perforce.freebsd.org/chv.cgi?CH=65299
Change 65299 by marcel at marcel_nfs on 2004/11/17 06:53:18
Remove UART_IPEND_* from dev/uart/uart_bus.h and have them
reincarnated as SER_INT_* in sys/serial.h. Adjust current
consumers of these defines.
The purpose of globalizing these defines this way is that
there's a handshake between different drivers WRT pending
interrupt sources and all drivers need to agree. For
example, puc(4) could in the near future query uart(4) for
any pending interrupts and have them handled in priority
order. Likewise, scc(4) can query the hardware to determine
which channel has what pending interrupts and call the
inferior driver to handle it. The inferior driver can be
uart(4), hdlc(4) or bsc(4).
Affected files ...
.. //depot/projects/uart/dev/uart/uart_bus.h#34 edit
.. //depot/projects/uart/dev/uart/uart_core.c#38 edit
.. //depot/projects/uart/dev/uart/uart_dev_i8251.c#4 edit
.. //depot/projects/uart/dev/uart/uart_dev_ns8250.c#32 edit
.. //depot/projects/uart/dev/uart/uart_dev_sab82532.c#33 edit
.. //depot/projects/uart/dev/uart/uart_dev_z8530.c#19 edit
.. //depot/projects/uart/dev/uart/uart_kbd_sun.c#2 edit
.. //depot/projects/uart/dev/uart/uart_tty.c#20 edit
.. //depot/projects/uart/sys/serial.h#2 edit
Differences ...
==== //depot/projects/uart/dev/uart/uart_bus.h#34 (text+ko) ====
@@ -42,21 +42,6 @@
#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
-/*
- * Interrupt sources (in priority order). See also uart_core.c
- * Note that the low order 16 bits are used to pass modem signals
- * from the hardware interrupt handler to the software interrupt
- * handler.
- */
-#define UART_IPEND_OVERRUN 0x010000
-#define UART_IPEND_BREAK 0x020000
-#define UART_IPEND_RXREADY 0x040000
-#define UART_IPEND_SIGCHG 0x080000
-#define UART_IPEND_TXIDLE 0x100000
-
-#define UART_IPEND_MASK 0x1f0000
-#define UART_IPEND_SIGMASK 0x00ffff
-
/* Received character status bits. */
#define UART_STAT_BREAK 0x0100
#define UART_STAT_FRAMERR 0x0200
==== //depot/projects/uart/dev/uart/uart_core.c#38 (text+ko) ====
@@ -91,7 +91,7 @@
}
#endif
if (sc->sc_opened) {
- atomic_set_32(&sc->sc_ttypend, UART_IPEND_BREAK);
+ atomic_set_32(&sc->sc_ttypend, SER_INT_BREAK);
swi_sched(sc->sc_softih, 0);
}
}
@@ -120,7 +120,7 @@
UART_RECEIVE(sc);
if (uart_rx_put(sc, UART_STAT_OVERRUN))
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
- atomic_set_32(&sc->sc_ttypend, UART_IPEND_RXREADY);
+ atomic_set_32(&sc->sc_ttypend, SER_INT_RXREADY);
swi_sched(sc->sc_softih, 0);
}
UART_FLUSH(sc, UART_FLUSH_RECEIVER);
@@ -148,7 +148,7 @@
}
#endif
if (sc->sc_opened) {
- atomic_set_32(&sc->sc_ttypend, UART_IPEND_RXREADY);
+ atomic_set_32(&sc->sc_ttypend, SER_INT_RXREADY);
swi_sched(sc->sc_softih, 0);
} else
sc->sc_rxput = sc->sc_rxget; /* Ignore received data. */
@@ -187,8 +187,8 @@
do {
old = sc->sc_ttypend;
new = old & ~UART_SIGMASK_STATE;
- new |= sig & UART_IPEND_SIGMASK;
- new |= UART_IPEND_SIGCHG;
+ new |= sig & SER_INT_SIGMASK;
+ new |= SER_INT_SIGCHG;
} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
if (sc->sc_opened)
swi_sched(sc->sc_softih, 0);
@@ -205,7 +205,7 @@
if (sc->sc_txbusy) {
sc->sc_txbusy = 0;
if (sc->sc_opened) {
- atomic_set_32(&sc->sc_ttypend, UART_IPEND_TXIDLE);
+ atomic_set_32(&sc->sc_ttypend, SER_INT_TXIDLE);
swi_sched(sc->sc_softih, 0);
}
}
@@ -218,15 +218,15 @@
int ipend;
while (!sc->sc_leaving && (ipend = UART_IPEND(sc)) != 0) {
- if (ipend & UART_IPEND_OVERRUN)
+ if (ipend & SER_INT_OVERRUN)
uart_intr_overrun(sc);
- if (ipend & UART_IPEND_BREAK)
+ if (ipend & SER_INT_BREAK)
uart_intr_break(sc);
- if (ipend & UART_IPEND_RXREADY)
+ if (ipend & SER_INT_RXREADY)
uart_intr_rxready(sc);
- if (ipend & UART_IPEND_SIGCHG)
+ if (ipend & SER_INT_SIGCHG)
uart_intr_sigchg(sc);
- if (ipend & UART_IPEND_TXIDLE)
+ if (ipend & SER_INT_TXIDLE)
uart_intr_txidle(sc);
}
}
==== //depot/projects/uart/dev/uart/uart_dev_i8251.c#4 (text+ko) ====
@@ -510,17 +510,17 @@
lsr = uart_getreg(bas, REG_LSR);
mtx_unlock_spin(&sc->sc_hwmtx);
if (lsr & LSR_OE)
- ipend |= UART_IPEND_OVERRUN;
+ ipend |= SER_INT_OVERRUN;
if (lsr & LSR_BI)
- ipend |= UART_IPEND_BREAK;
+ ipend |= SER_INT_BREAK;
if (lsr & LSR_RXRDY)
- ipend |= UART_IPEND_RXREADY;
+ ipend |= SER_INT_RXREADY;
} else {
mtx_unlock_spin(&sc->sc_hwmtx);
if (iir & IIR_TXRDY)
- ipend |= UART_IPEND_TXIDLE;
+ ipend |= SER_INT_TXIDLE;
else
- ipend |= UART_IPEND_SIGCHG;
+ ipend |= SER_INT_SIGCHG;
}
return ((sc->sc_leaving) ? 0 : ipend);
}
==== //depot/projects/uart/dev/uart/uart_dev_ns8250.c#32 (text+ko) ====
@@ -555,17 +555,17 @@
lsr = uart_getreg(bas, REG_LSR);
mtx_unlock_spin(&sc->sc_hwmtx);
if (lsr & LSR_OE)
- ipend |= UART_IPEND_OVERRUN;
+ ipend |= SER_INT_OVERRUN;
if (lsr & LSR_BI)
- ipend |= UART_IPEND_BREAK;
+ ipend |= SER_INT_BREAK;
if (lsr & LSR_RXRDY)
- ipend |= UART_IPEND_RXREADY;
+ ipend |= SER_INT_RXREADY;
} else {
mtx_unlock_spin(&sc->sc_hwmtx);
if (iir & IIR_TXRDY)
- ipend |= UART_IPEND_TXIDLE;
+ ipend |= SER_INT_TXIDLE;
else
- ipend |= UART_IPEND_SIGCHG;
+ ipend |= SER_INT_SIGCHG;
}
return ((sc->sc_leaving) ? 0 : ipend);
}
==== //depot/projects/uart/dev/uart/uart_dev_sab82532.c#33 (text+ko) ====
@@ -545,15 +545,15 @@
ipend = 0;
if (isr1 & SAB_ISR1_BRKT)
- ipend |= UART_IPEND_BREAK;
+ ipend |= SER_INT_BREAK;
if (isr0 & SAB_ISR0_RFO)
- ipend |= UART_IPEND_OVERRUN;
+ ipend |= SER_INT_OVERRUN;
if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
- ipend |= UART_IPEND_RXREADY;
+ ipend |= SER_INT_RXREADY;
if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
- ipend |= UART_IPEND_SIGCHG;
+ ipend |= SER_INT_SIGCHG;
if (isr1 & SAB_ISR1_ALLS)
- ipend |= UART_IPEND_TXIDLE;
+ ipend |= SER_INT_TXIDLE;
return (ipend);
}
==== //depot/projects/uart/dev/uart/uart_dev_z8530.c#19 (text+ko) ====
@@ -306,7 +306,7 @@
z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
z8530->tpc &= ~(TPC_DTR|TPC_RTS);
}
- z8530->txidle = 1; /* Report UART_IPEND_TXIDLE. */
+ z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
sc->sc_rxfifosz = 3;
sc->sc_txfifosz = 1;
@@ -401,24 +401,24 @@
bes = uart_getmreg(bas, RR_BES);
if (bes & BES_BRK) {
uart_setreg(bas, REG_CTRL, CR_RSTXSI);
- ipend |= UART_IPEND_BREAK;
+ ipend |= SER_INT_BREAK;
}
if (bes & BES_TXE && z8530->txidle) {
uart_setreg(bas, REG_CTRL, CR_RSTTXI);
- ipend |= UART_IPEND_TXIDLE;
- z8530->txidle = 0; /* Suppress UART_IPEND_TXIDLE. */
+ ipend |= SER_INT_TXIDLE;
+ z8530->txidle = 0; /* Suppress SER_INT_TXIDLE. */
}
if (bes & BES_RXA)
- ipend |= UART_IPEND_RXREADY;
+ ipend |= SER_INT_RXREADY;
sig = sc->sc_hwsig;
SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
if (sig & UART_SIGMASK_DELTA)
- ipend |= UART_IPEND_SIGCHG;
+ ipend |= SER_INT_SIGCHG;
src = uart_getmreg(bas, RR_SRC);
if (src & SRC_OVR) {
uart_setreg(bas, REG_CTRL, CR_RSTERR);
- ipend |= UART_IPEND_OVERRUN;
+ ipend |= SER_INT_OVERRUN;
}
mtx_unlock_spin(&sc->sc_hwmtx);
return (ipend);
@@ -547,7 +547,7 @@
uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
uart_barrier(bas);
sc->sc_txbusy = 1;
- z8530->txidle = 1; /* Report UART_IPEND_TXIDLE again. */
+ z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
}
==== //depot/projects/uart/dev/uart/uart_kbd_sun.c#2 (text+ko) ====
@@ -248,10 +248,10 @@
return;
pend = atomic_readandclear_32(&sc->sc_uart->sc_ttypend);
- if (!(pend & UART_IPEND_MASK))
+ if (!(pend & SER_INT_MASK))
return;
- if (pend & UART_IPEND_RXREADY) {
+ if (pend & SER_INT_RXREADY) {
if (KBD_IS_ACTIVE(&sc->sc_kbd) && KBD_IS_BUSY(&sc->sc_kbd)) {
sc->sc_kbd.kb_callback.kc_func(&sc->sc_kbd,
KBDIO_KEYINPUT, sc->sc_kbd.kb_callback.kc_arg);
==== //depot/projects/uart/dev/uart/uart_tty.c#20 (text+ko) ====
@@ -306,12 +306,12 @@
return;
pend = atomic_readandclear_32(&sc->sc_ttypend);
- if (!(pend & UART_IPEND_MASK))
+ if (!(pend & SER_INT_MASK))
return;
tp = sc->sc_u.u_tty.tp;
- if (pend & UART_IPEND_RXREADY) {
+ if (pend & SER_INT_RXREADY) {
while (!uart_rx_empty(sc) && !(tp->t_state & TS_TBLOCK)) {
xc = uart_rx_get(sc);
c = xc & 0xff;
@@ -323,13 +323,13 @@
}
}
- if (pend & UART_IPEND_BREAK) {
+ if (pend & SER_INT_BREAK) {
if (tp != NULL && !(tp->t_iflag & IGNBRK))
ttyld_rint(tp, 0);
}
- if (pend & UART_IPEND_SIGCHG) {
- sig = pend & UART_IPEND_SIGMASK;
+ if (pend & SER_INT_SIGCHG) {
+ sig = pend & SER_INT_SIGMASK;
if (sig & SER_DDCD)
ttyld_modem(tp, sig & SER_DCD);
if ((sig & SER_DCTS) && (tp->t_cflag & CCTS_OFLOW) &&
@@ -342,7 +342,7 @@
}
}
- if (pend & UART_IPEND_TXIDLE) {
+ if (pend & SER_INT_TXIDLE) {
tp->t_state &= ~TS_BUSY;
ttyld_start(tp);
}
==== //depot/projects/uart/sys/serial.h#2 (text+ko) ====
@@ -61,4 +61,21 @@
#define SER_DRI SER_DELTA(SER_RI)
#define SER_DDSR SER_DELTA(SER_DSR)
+/*
+ * Specification of interrupt sources typical for serial ports. These are
+ * useful when some umbrella driver like scc(4) has enough knowledge of
+ * the hardware to obtain the set of pending interrupts but does not itself
+ * handle the interrupt. Each interrupt source can be given an interrupt
+ * resource for which inferior drivers can install handlers. The lower 16
+ * bits are kept free for the signals above.
+ */
+#define SER_INT_OVERRUN 0x010000
+#define SER_INT_BREAK 0x020000
+#define SER_INT_RXREADY 0x040000
+#define SER_INT_SIGCHG 0x080000
+#define SER_INT_TXIDLE 0x100000
+
+#define SER_INT_MASK 0xff0000
+#define SER_INT_SIGMASK 0x00ffff
+
#endif /* !_SYS_SERIAL_H_ */
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