PERFORCE change 48374 for review
Juli Mallett
jmallett at FreeBSD.org
Sun Mar 7 15:24:35 PST 2004
http://perforce.freebsd.org/chv.cgi?CH=48374
Change 48374 by jmallett at jmallett_oingo on 2004/03/07 15:24:10
Attempt to cleanup and stuff. Like, using a table.
Affected files ...
.. //depot/projects/mips/sys/mips/mips/exception.S#15 edit
Differences ...
==== //depot/projects/mips/sys/mips/mips/exception.S#15 (text+ko) ====
@@ -29,6 +29,40 @@
#define VEND(x) \
_VEND(x)
+ExceptionHandlerTable:
+ .dword GenericException /* Int */
+ .dword GenericException /* TLBMod */
+ .dword XTLBMissVector /* TLBL */
+ .dword XTLBMissVector /* TLBS */
+ .dword GenericException /* AdEL */
+ .dword GenericException /* AdES */
+ .dword GenericException /* IBE */
+ .dword GenericException /* DBE */
+ .dword GenericException /* Sys */
+ .dword GenericException /* Bp */
+ .dword GenericException /* RI */
+ .dword GenericException /* CpU */
+ .dword GenericException /* Ov */
+ .dword GenericException /* Tr */
+ .dword GenericException /* VCEI */
+ .dword GenericException /* FPE */
+ .dword GenericException /* Res (16) */
+ .dword GenericException /* Res (17) */
+ .dword GenericException /* Res (18) */
+ .dword GenericException /* Res (19) */
+ .dword GenericException /* Res (20) */
+ .dword GenericException /* Res (21) */
+ .dword GenericException /* Res (22) */
+ .dword GenericException /* WATCH */
+ .dword GenericException /* Res (24) */
+ .dword GenericException /* Res (25) */
+ .dword GenericException /* Res (26) */
+ .dword GenericException /* Res (27) */
+ .dword GenericException /* Res (28) */
+ .dword GenericException /* Res (29) */
+ .dword GenericException /* Res (30) */
+ .dword GenericException /* VCED */
+
.text
.set noreorder
@@ -41,6 +75,20 @@
*/
LEAF(ExceptionVector)
.set noat
+ mfc0 k0, MIPS_COP_0_CAUSE
+ and k0, MIPS_CR_EXC_CODE
+ dsrl k0, MIPS_CR_EXC_CODE_SHIFT
+ dsll k0, 3 /* Index 64-bits. */
+ dla k1, ExceptionHandlerTable
+ daddu k1, k0
+ ld k1, 0(k1)
+ jr k1
+ nop
+ .set at
+VEND(ExceptionVector)
+
+LEAF(GenericException)
+ .set noat
dsubu sp, sp, TF_SIZE
dla k0, 1f
j exception_save_registers
@@ -73,61 +121,35 @@
daddu sp, sp, TF_SIZE
eret
.set at
-VEND(ExceptionVector)
+END(GenericException)
LEAF(CacheVector)
.set noat
-
- dsubu sp, sp, TF_SIZE
- dla k0, 1f
- j exception_save_registers
- move k1, sp
-1:
- /*
- * No turning back, and nothing we can do. Just call into
- * trap and let it tell the user lovely things about how bad
- * their cache has been,
- */
- mfc0 a1, MIPS_COP_0_CAUSE
- dmfc0 a2, MIPS_COP_0_BAD_VADDR
- jal trap
- move a0, k1
-
- jal exception_restore_registers
- move a0, sp
- daddu sp, sp, TF_SIZE
+ dla k0, __panic
+ li a0, 0
+ li a1, 0
+ dmtc0 k0, MIPS_COP_0_EXC_PC
+ dla a2, 1f
eret
.set at
VEND(CacheVector)
+ .data
+1: .asciiz "CacheVector"
+ .text
LEAF(TLBMissVector)
.set noat
-#if R4600
- j XTLBMissVector
- nop
-#else
- dsubu sp, sp, TF_SIZE
- dla k0, 1f
- j exception_save_registers
- move k1, sp
-1:
- /*
- * No turning back, and nothing we can do. Just call into
- * trap and let it tell the user lovely things about how bad
- * their cache has been,
- */
- mfc0 a1, MIPS_COP_0_CAUSE
- dmfc0 a2, MIPS_COP_0_BAD_VADDR
- jal trap
- move a0, k1
-
- jal exception_restore_registers
- move a0, sp
- daddu sp, sp, TF_SIZE
+ dla k0, __panic
+ li a0, 0
+ li a1, 0
+ dmtc0 k0, MIPS_COP_0_EXC_PC
+ dla a2, 1f
eret
-#endif
.set at
VEND(TLBMissVector)
+ .data
+1: .asciiz "32-bit TLB Miss Vector"
+ .text
/*
* XXX kernel only. For now that makes sense.
@@ -136,6 +158,7 @@
.set noat
dmfc0 k0, MIPS_COP_0_BAD_VADDR
dli k1, MIPS_XKSEG_START
+ tltu k0, k1
dsubu k0, k1
/*
* Shift right logical to get a page index, but leaving
@@ -169,39 +192,6 @@
VEND(XTLBMissVector)
/*
- * Handle an interrupt. Return into panic, for now.
- */
-LEAF(Interrupt)
- .set noat
- mfc0 k1, MIPS_COP_0_CAUSE
- li a0, 0
- li a1, 0
- dla k0, __panic
- dmtc0 k0, MIPS_COP_0_EXC_PC
- dla a2, 1f
- move a3, k1
- eret
- .set at
-END(Interrupt)
- .data
-1: .asciiz "Interrupt, cause: %lx\n"
- .text
-
-/*
- * Handle VCED.
- */
-LEAF(VCED)
- .set noat
- dmfc0 k0, MIPS_COP_0_BAD_VADDR
- li k1, -16
- and k0, k1
- cache (CACHE_R4K_SD | CACHEOP_R4K_HIT_WB_INV), 0(k0)
- cache (CACHE_R4K_D | CACHEOP_R4K_HIT_INV), 0(k0)
- eret
- .set at
-END(VCED)
-
-/*
* Restore registers from a trapframe pointed to in k1, returning to ra
* that is passed in, and kept in k0.
*/
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