PERFORCE change 55005 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=55005

Change 55005 by jmallett at jmallett_oingo on 2004/06/15 11:02:02

	Dole out cached addresses, add some cache writebacks in clever locations.
	Yay a TLB abstraction to hide most of this behind.  Now I just have to
	hide the direct mapping stuff behind a TLB interface.
	
	This gets the Indigo2 (real) to run to mountroot>

Affected files ...

.. //depot/projects/mips/sys/mips/conf/INDY#13 edit
.. //depot/projects/mips/sys/mips/mips/pmap.c#38 edit
.. //depot/projects/mips/sys/mips/mips/tlb.c#25 edit

Differences ...

==== //depot/projects/mips/sys/mips/conf/INDY#13 (text+ko) ====

@@ -12,7 +12,7 @@
 
 makeoptions	MIPSOPTS=-mips3		#Build for a MIPS III
 
-makeoptions	TEXTADDR=0xA8069000	#Indy
+makeoptions	TEXTADDR=0x88069000	#Indy
 
 # Platform support
 platform	sgimips			#SGI MIPS systems.

==== //depot/projects/mips/sys/mips/mips/pmap.c#38 (text+ko) ====

@@ -247,7 +247,7 @@
 	pa = phys_avail[0];
 	phys_avail[0] += size;
 
-	va = MIPS_PHYS_TO_KSEG1(pa);
+	va = MIPS_PHYS_TO_KSEG0(pa);
 	bzero((caddr_t) va, size);
 	return va;
 }
@@ -330,7 +330,7 @@
 			break;
 	}
 
-	va = (void *)MIPS_PHYS_TO_KSEG1(m->phys_addr);
+	va = (void *)MIPS_PHYS_TO_KSEG0(m->phys_addr);
 	if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
 		bzero(va, PAGE_SIZE);
 	return (va);
@@ -341,7 +341,7 @@
 {
 	vm_page_t m;
 
-	m = PHYS_TO_VM_PAGE(MIPS_KSEG1_TO_PHYS((vm_offset_t)mem));
+	m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS((vm_offset_t)mem));
 	vm_page_lock_queues();
 	vm_page_free(m);
 	vm_page_unlock_queues();
@@ -519,6 +519,8 @@
 
 	if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
 		pa = MIPS_KSEG1_TO_PHYS(va);
+	else if (va >= MIPS_KSEG0_START && va <= MIPS_KSEG0_END)
+		pa = MIPS_KSEG0_TO_PHYS(va);
 	else
 		pa = pmap_extract(kernel_pmap, va);
 	return pa;
@@ -646,7 +648,7 @@
 #if 0 /* XXX notyet, need pmap_extract etc., to love us. */
 	return MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_UC, start);
 #endif
-	return MIPS_PHYS_TO_KSEG1(start);
+	return MIPS_PHYS_TO_KSEG0(start);
 }
 
 void
@@ -696,7 +698,7 @@
 	vm_page_unlock_queues();
 	VM_OBJECT_UNLOCK(pmap->pm_pteobj);
 
-	pmap->pm_lev1 = (pt_entry_t*) MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(lev1pg));
+	pmap->pm_lev1 = (pt_entry_t*) MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(lev1pg));
 
 	/* install self-referential address mapping entry (not PG_ASM) */
 	pmap->pm_lev1[PTLEV1I] = pmap_phys_to_pte(VM_PAGE_TO_PHYS(lev1pg))
@@ -1251,7 +1253,7 @@
 void
 pmap_zero_page(vm_page_t m)
 {
-	vm_offset_t va = MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(m));
+	vm_offset_t va = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(m));
 	bzero((caddr_t) va, PAGE_SIZE);
 }
 
@@ -1267,7 +1269,7 @@
 void
 pmap_zero_page_area(vm_page_t m, int off, int size)
 {
-	vm_offset_t va = MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(m));
+	vm_offset_t va = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(m));
 	bzero((char *)(caddr_t)va + off, size);
 }
 
@@ -1281,7 +1283,7 @@
 void
 pmap_zero_page_idle(vm_page_t m)
 {
-	vm_offset_t va = MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(m));
+	vm_offset_t va = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(m));
 	bzero((caddr_t) va, PAGE_SIZE);
 }
 
@@ -1295,8 +1297,8 @@
 void
 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
 {
-	vm_offset_t src = MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(msrc));
-	vm_offset_t dst = MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(mdst));
+	vm_offset_t src = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(msrc));
+	vm_offset_t dst = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(mdst));
 	bcopy((caddr_t) src, (caddr_t) dst, PAGE_SIZE);
 }
 

==== //depot/projects/mips/sys/mips/mips/tlb.c#25 (text+ko) ====

@@ -52,6 +52,7 @@
 
 #include <sys/user.h>
 
+#include <machine/cache.h>
 #include <machine/locore.h>
 #include <machine/md_var.h>
 #include <machine/tlb.h>
@@ -125,12 +126,14 @@
 	pte = tlb_pte_find(pmap->pm_lev1, va);
 	if (pte_valid(pte))
 		tlb_invalidate_page(va);
+	else
+		mips_dcache_wbinv_range_index(va, PAGE_SIZE);
 	if ((bits & PG_V) == 0)
 		panic("pmap %p entering invalid mapping for va %lx to pa %lx [%lx]",
 		       pmap, (u_long)va, (u_long)pa, (u_long)bits);
 	*pte &= PG_G;
 	*pte |= MIPS_PA_TO_PFN(pa) | bits;
-	*pte |= PG_C_UNCACHED;
+	*pte |= PG_C_CNC; /* Cacheable noncoherent. */
 }
 
 void
@@ -220,6 +223,7 @@
 	i = mips_rd_index();
 	if (i >= 0)
 		tlb_invalidate_one(i);
+	mips_dcache_wbinv_range_index(va, PAGE_SIZE);
 }
 
 /*