PERFORCE change 54246 for review
Juli Mallett
jmallett at FreeBSD.org
Sun Jun 6 01:42:34 GMT 2004
http://perforce.freebsd.org/chv.cgi?CH=54246
Change 54246 by jmallett at jmallett_oingo on 2004/06/06 01:41:37
Catching up with changed code.
Affected files ...
.. //depot/projects/mips/sys/mips/mips/locore.S#12 edit
Differences ...
==== //depot/projects/mips/sys/mips/mips/locore.S#12 (text+ko) ====
@@ -61,9 +61,8 @@
li t0, MIPS_SR_KX | MIPS_SR_COP_1_BIT
/*
- * Read coprocessor 0 status register, clear bits not
- * preserved (namely, clearing interrupt bits), and set
- * bits we want to explicitly set.
+ * Read coprocessor 0 status register, and set bits we want to
+ * explicitly set.
*/
mfc0 t1, MIPS_COP_0_STATUS
or t1, t0
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