PERFORCE change 54236 for review
Scott Long
scottl at FreeBSD.org
Sat Jun 5 19:20:05 GMT 2004
http://perforce.freebsd.org/chv.cgi?CH=54236
Change 54236 by scottl at scottl-esp-sparc64 on 2004/06/05 19:19:04
Convert the lsi64854 driver to busdma. This covers both the
parallel port and the scsi sides. Completely untested, but it
compiles cleanly =-)
Affected files ...
.. //depot/projects/scottl-esp/src/sys/dev/esp/lsi64854.c#4 edit
.. //depot/projects/scottl-esp/src/sys/dev/esp/lsi64854var.h#5 edit
Differences ...
==== //depot/projects/scottl-esp/src/sys/dev/esp/lsi64854.c#4 (text+ko) ====
@@ -80,8 +80,6 @@
/*
* Finish attaching this DMA device.
* Front-end must fill in these fields:
- * sc_bustag
- * sc_dmatag
* sc_regs
* sc_burst
* sc_channel (one of SCSI, ENET, PP)
@@ -113,8 +111,22 @@
sc->reset = lsi64854_reset;
/* Allocate a dmamap */
- if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ,
- 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) {
+ if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */
+ 1, 0, /* algnment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MAX_DMA_SZ, /* maxsize */
+ 1, /* nsegments */
+ MAX_DMA_SZ, /* maxsegsize */
+ BUS_DMA_ALLOCNOW, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->sc_buffer_dmat)) {
+ printf("%s: can't allocate buffer DMA tag\n", sc->dv_name);
+ return;
+ }
+
+ if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) {
printf("%s: DMA map create failed\n", sc->dv_name);
return;
}
@@ -222,9 +234,9 @@
/*
* XXX is sync needed?
+ if (sc->sc_dmamap->dm_nsegs > 0)
+ bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
*/
- if (sc->sc_dmamap->dm_nsegs > 0)
- bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
if (sc->sc_rev == DMAREV_HME)
L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
@@ -283,6 +295,22 @@
DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
}
+static void
+lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ struct lsi64854_softc *sc;
+
+ sc = (struct lsi64854_softc *)arg;
+
+ if (nseg != 1)
+ panic("%s: cannot map %d segments\n", sc->dv_name, nseg);
+
+ bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
+ BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
+ bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
+ segs[0].ds_addr);
+}
+
#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
/*
@@ -305,6 +333,7 @@
#endif
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
+ sc->sc_datain = datain;
/*
* the rules say we cannot transfer more than the limit
@@ -329,26 +358,18 @@
/* Program the DMA address */
if (sc->sc_dmasize) {
- sc->sc_dvmaaddr = *sc->sc_dmaaddr;
- if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
+ if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
- NULL /* kernel address */,
- BUS_DMA_NOWAIT | BUS_DMA_STREAMING))
+ lsi64854_map_scsi, sc, 0) != 0)
panic("%s: cannot allocate DVMA address", sc->dv_name);
- bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
- datain
- ? BUS_DMASYNC_PREREAD
- : BUS_DMASYNC_PREWRITE);
- bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
- sc->sc_dmamap->dm_segs[0].ds_addr);
}
if (sc->sc_rev == DMAREV_ESC) {
/* DMA ESC chip bug work-around */
long bcnt = sc->sc_dmasize;
long eaddr = bcnt + (long)*sc->sc_dmaaddr;
- if ((eaddr & PGOFSET) != 0)
- bcnt = roundup(bcnt, PAGE_SIZE);
+ if ((eaddr & PAGE_MASK_8K) != 0)
+ bcnt = roundup(bcnt, PAGE_SIZE_8K);
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
bcnt);
}
@@ -384,19 +405,17 @@
{
struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client;
- char bits[64];
int trans, resid;
u_int32_t csr;
csr = L64854_GCSR(sc);
- DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->dv_name,
+ DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
- bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits))));
+ csr, DDMACSR_BITS));
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
- printf("%s: error: csr=%s\n", sc->dv_name,
- bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits)));
+ printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS);
csr &= ~D_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE|D_SLAVE_ERR;
@@ -478,13 +497,15 @@
? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
+#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
- bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
+ bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
- bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
+ bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
+#endif
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
@@ -509,7 +530,6 @@
void *arg;
{
struct lsi64854_softc *sc = arg;
- char bits[64];
u_int32_t csr;
static int dodrain = 0;
int rv;
@@ -520,8 +540,7 @@
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
- printf("%s: error: csr=%s\n", sc->dv_name,
- bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits)));
+ printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS);
csr &= ~L64854_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= E_INVALIDATE|E_SLAVE_ERR;
@@ -536,12 +555,32 @@
csr |= E_DRAIN;
L64854_SCSR(sc, csr);
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
- delay(1);
+ DELAY(1);
}
return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
}
+static void
+lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+ struct lsi64854_softc *sc;
+
+ sc = (struct lsi64854_softc *)arg;
+
+ if (nsegs != 1)
+ panic("%s: cannot map %d segments\n", sc->dv_name, nsegs);
+
+ bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain
+ ? BUS_DMASYNC_PREREAD
+ : BUS_DMASYNC_PREWRITE);
+ bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
+ segs[0].ds_addr);
+
+ bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
+ sc->sc_dmasize);
+}
+
/*
* setup a DMA transfer
*/
@@ -559,6 +598,7 @@
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
+ sc->sc_datain = datain;
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name,
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
@@ -575,22 +615,11 @@
/* Program the DMA address */
if (sc->sc_dmasize) {
- sc->sc_dvmaaddr = *sc->sc_dmaaddr;
- if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
+ if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
- NULL /* kernel address */,
- BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/))
+ lsi64854_map_pp, sc, 0) != 0)
panic("%s: pp cannot allocate DVMA address",
sc->dv_name);
- bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
- datain
- ? BUS_DMASYNC_PREREAD
- : BUS_DMASYNC_PREWRITE);
- bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
- sc->sc_dmamap->dm_segs[0].ds_addr);
-
- bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
- sc->sc_dmasize);
}
/* Setup DMA control register */
@@ -623,21 +652,20 @@
void *arg;
{
struct lsi64854_softc *sc = arg;
- char bits[64];
int ret, trans, resid = 0;
u_int32_t csr;
csr = L64854_GCSR(sc);
- DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->dv_name,
+ DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name,
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
- bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits))));
+ csr, PDMACSR_BITS));
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
L64854_REG_CNT);
- printf("%s: pp error: resid %d csr=%s\n", sc->dv_name, resid,
- bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits)));
+ printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid,
+ csr, PDMACSR_BITS);
csr &= ~P_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= P_INVALIDATE|P_SLAVE_ERR;
@@ -665,13 +693,15 @@
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
+#if 0 /* XXX */
if (sc->sc_dmamap->dm_nsegs > 0) {
- bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
+ bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
(csr & D_WRITE) != 0
? BUS_DMASYNC_POSTREAD
: BUS_DMASYNC_POSTWRITE);
- bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
+ bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
}
+#endif
return (ret != 0);
}
==== //depot/projects/scottl-esp/src/sys/dev/esp/lsi64854var.h#5 (text+ko) ====
@@ -55,9 +55,10 @@
int sc_active; /* DMA active ? */
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
-#ifdef NOT_NEEDED
- caddr_t sc_dvmaaddr; /* DVMA cookie */
-#endif
+
+ bus_dma_tag_t sc_parent_dmat;
+ bus_dma_tag_t sc_buffer_dmat;
+ int sc_datain;
size_t sc_dmasize;
caddr_t *sc_dmaaddr;
size_t *sc_dmalen;
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