PERFORCE change 40943 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=40943

Change 40943 by jmallett at jmallett_sprout on 2003/10/30 22:28:24

	First stab at entryhi region stuff, probably fairly wrong.

Affected files ...

.. //depot/projects/mips/sys/mips/include/pte.h#10 edit
.. //depot/projects/mips/sys/mips/mips/mips_subr.S#13 edit
.. //depot/projects/mips/sys/mips/mips/tlb.c#3 edit

Differences ...

==== //depot/projects/mips/sys/mips/include/pte.h#10 (text+ko) ====

@@ -67,6 +67,9 @@
  * bit 12 to bit 8 there is a 5-bit 0 field.  Low byte is ASID.
  */
 #define	MIPS_HI_R_SHIFT		62
+#define	MIPS_HI_R_USER		(0x00 << MIPS_HI_R_SHIFT)
+#define	MIPS_HI_R_SUPERVISOR	(0x01 << MIPS_HI_R_SHIFT)
+#define	MIPS_HI_R_KERNEL	(0x11 << MIPS_HI_R_SHIFT)
 #define	MIPS_HI_FILL_SHIFT	40
 #define	MIPS_HI_VPN2_SHIFT	13
 #define	MIPS_HI_VPN2_BMASK	0xFFFFFFE
@@ -75,10 +78,16 @@
 
 /*
  * TLB page bits that aren't really flags:
+ * 	R0:	Region 0, user
+ * 	R1:	Region 1, supervisor
+ * 	R3:	Region 3, kernel
  * 	ODDPG:	Is this page odd?	! XXX NetBSD compat
  * 	HVPN:	Hardware VPN mask	! XXX NetBSD compat
  * 	ASID:	Address space ID
  */
+#define	PG_R0		MIPS_HI_R_USER
+#define	PG_R1		MIPS_HI_R_SUPERVISOR
+#define	PG_R3		MIPS_HI_R_KERNEL
 #define	PG_ODDPG	0x00001000
 #define	PG_HVPN		MIPS_HI_VPN2_MASK
 #define	PG_ASID		0x000000ff

==== //depot/projects/mips/sys/mips/mips/mips_subr.S#13 (text+ko) ====

@@ -368,7 +368,7 @@
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 	COP0_SYNC
 
-	li	v0, (PG_HVPN | PG_ASID)
+	li	v0, (PG_HVPN | PG_ASID | PG_R3) # XXX assumes Region3
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# save current ASID
 	mfc0	t3, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
 	and	a0, a0, v0			# make sure valid entryHi

==== //depot/projects/mips/sys/mips/mips/tlb.c#3 (text+ko) ====

@@ -137,7 +137,8 @@
 {
 	va &= ~PAGE_SIZE;
 	critical_enter();
-	mips_wr_entryhi(MIPS_HI_VA_TO_VPN2(va) /* XXX | ASID */);
+	/* XXX assumes kernel region - region 3. */
+	mips_wr_entryhi(MIPS_HI_R_KERNEL | MIPS_HI_VA_TO_VPN2(va) /* XXX | ASID */);
 	mips_wr_entrylo0(pte0);
 	mips_wr_entrylo1(pte1);
 	mips_tlbwr();