PERFORCE change 42106 for review
Juli Mallett
jmallett at FreeBSD.org
Tue Nov 11 22:34:28 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=42106
Change 42106 by jmallett at jmallett_dalek on 2003/11/11 22:33:36
Remove TLBRead, struct tlb, struct kernframe, other cruft.
Affected files ...
.. //depot/projects/mips/sys/mips/include/locore.h#13 edit
.. //depot/projects/mips/sys/mips/include/pte.h#15 edit
.. //depot/projects/mips/sys/mips/mips/db_interface.c#10 edit
.. //depot/projects/mips/sys/mips/mips/genassym.c#9 edit
.. //depot/projects/mips/sys/mips/mips/mips_subr.S#18 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/locore.h#13 (text+ko) ====
@@ -31,9 +31,6 @@
struct tlb;
-void mips64_TLBRead(int, struct tlb *);
-void mips64_wbflush(void);
-
uint32_t mipsNN_cp0_config1_read(void);
void mipsNN_cp0_config1_write(uint32_t);
uint32_t mipsNN_cp0_config2_read(void);
@@ -62,28 +59,8 @@
#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
#ifdef _KERNEL
-/*
- * Global variables used to communicate CPU type, and parameters
- * such as cache size, from locore to higher-level code (e.g., pmap).
- */
-
-
#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG
void mips_machdep_cache_config(void);
#endif
-
-/*
- * Stack frame for kernel traps. four args passed in registers.
- * A trapframe is pointed to by the 5th arg, and a dummy sixth argument
- * is used to avoid alignment problems
- */
-
-struct kernframe {
- register_t cf_args[4 + 1];
- register_t cf_pad; /* (for 8 word alignment) */
- register_t cf_sp;
- register_t cf_ra;
- struct trapframe cf_frame;
-};
#endif /* _KERNEL */
#endif /* _MIPS_LOCORE_H */
==== //depot/projects/mips/sys/mips/include/pte.h#15 (text+ko) ====
@@ -17,25 +17,8 @@
*/
#ifndef LOCORE
typedef unsigned long pt_entry_t;
-#else
-#define PTESIZE 64
#endif
-#ifndef LOCORE
-/*
- * Structure defining the whole of the TLB.
- * XXX This is for NetBSD compat, and I really want to move away from
- * this sort of thing. Badly.
- */
-struct tlb {
- uint32_t tlb_mask; /* PageMask */
- uint32_t tlb_padding; /* alignment :( */
- register_t tlb_hi; /* EntryHi */
- register_t tlb_lo0; /* EntryLo0 */
- register_t tlb_lo1; /* EntryLo1 */
-};
-#endif /* LOCORE */
-
/*
* TLB and PTE management. Most things operate within the context of
* EntryLo0,1. Things which work with EntryHi have a HI in their name
==== //depot/projects/mips/sys/mips/mips/db_interface.c#10 (text+ko) ====
@@ -279,28 +279,32 @@
DB_COMMAND(tlb, db_tlbdump_cmd)
{
+ u_long hi;
+ u_long lo[2];
+ u_long pm;
+ int i;
- if (MIPS_HAS_R4K_MMU) {
- struct tlb tlb;
- int i;
+ for (i = 0; i < mips_num_tlb_entries; i++) {
+ mips_wr_index(i);
+ mips_tlbr();
+ hi = mips_rd_entryhi();
+ lo[0] = mips_rd_entrylo0();
+ lo[1] = mips_rd_entrylo1();
+ pm = mips_rd_pagemask();
- for (i = 0; i < mips_num_tlb_entries; i++) {
- mips64_TLBRead(i, &tlb);
- db_printf("TLB%c%2d Hi 0x%016lx ",
- (tlb.tlb_lo0 | tlb.tlb_lo1) & PG_V ? ' ' : '*',
- i, tlb.tlb_hi);
- db_printf("Lo0=0x%016lx %c%c attr %lx ",
- MIPS_PFN_TO_PA(tlb.tlb_lo0),
- (tlb.tlb_lo0 & PG_D) ? 'D' : ' ',
- (tlb.tlb_lo0 & PG_G) ? 'G' : ' ',
- (tlb.tlb_lo0 >> 3) & 7);
- db_printf("Lo1=0x%016lx %c%c attr %lx sz=%x\n",
- MIPS_PFN_TO_PA(tlb.tlb_lo1),
- (tlb.tlb_lo1 & PG_D) ? 'D' : ' ',
- (tlb.tlb_lo1 & PG_G) ? 'G' : ' ',
- (tlb.tlb_lo1 >> 3) & 7,
- tlb.tlb_mask);
- }
+ db_printf("TLB %c %2d Hi 0x%016lx ",
+ (lo[0] | lo[1]) & PG_V ? 'V' : '*', i, hi);
+ db_printf("Lo0=0x%016lx %c%c attr %lx ",
+ MIPS_PFN_TO_PA(lo[0]),
+ (lo[0] & PG_D) ? 'D' : ' ',
+ (lo[0] & PG_G) ? 'G' : ' ',
+ (lo[0] >> 3) & 7);
+ db_printf("Lo1=0x%016lx %c%c attr %lx ",
+ MIPS_PFN_TO_PA(lo[1]),
+ (lo[1] & PG_D) ? 'D' : ' ',
+ (lo[1] & PG_G) ? 'G' : ' ',
+ (lo[1] >> 3) & 7);
+ db_printf("sz=%#lx\n", pm);
}
}
==== //depot/projects/mips/sys/mips/mips/genassym.c#9 (text+ko) ====
@@ -140,14 +140,6 @@
ASSYM(FRAME_FP31 sizeof(mips_fpreg_t) * 31);
#endif
-ASSYM(KERNFRAME_SIZ, sizeof(struct kernframe));
-ASSYM(KERNFRAME_ARG5, offsetof(struct kernframe, cf_args[4]));
-ASSYM(KERNFRAME_ARG6, offsetof(struct kernframe, cf_args[5]));
-ASSYM(KERNFRAME_SP, offsetof(struct kernframe, cf_sp));
-ASSYM(KERNFRAME_RA, offsetof(struct kernframe, cf_ra));
-
-ASSYM(TF_BASE, offsetof(struct kernframe, cf_frame));
-
ASSYM(TF_SIZE, sizeof(struct trapframe));
ASSYM(TF_REG_AST, offsetof(struct trapframe, tf_regs[TF_AST]));
ASSYM(TF_REG_V0, offsetof(struct trapframe, tf_regs[TF_V0]));
==== //depot/projects/mips/sys/mips/mips/mips_subr.S#18 (text+ko) ====
@@ -130,105 +130,3 @@
#include "assym.s"
-#define _SLL dsll
-#define _SRL dsrl
-#define WIRED_SHIFT 34
-
-/*
- * Use correct-sized m?c0/dm?c0 opcodes.
- */
-#define _MFC0 dmfc0
-#define _MTC0 dmtc0
-
-/*
- * CPP function renaming macros.
- */
-#ifdef __STDC__
-#define MIPSX(name) mips64_ ## name
-#else
-#define MIPSX(name) mips64_/**/name
-#endif
-
-/*
- * XXX We need a cleaner way of handling the instruction hazards of
- * the various processors. Here are the relevant rules for the QED 52XX:
- * tlbw[ri] -- two integer ops beforehand
- * tlbr -- two integer ops beforehand
- * tlbp -- two integer ops beforehand
- * mtc0 [PageMask,EntryHi,Cp0] -- two integer ops afterwards
- * changing JTLB -- two integer ops afterwards
- * mtc0 [EPC,ErrorEPC,Status] -- two int ops afterwards before eret
- * config.k0 -- five int ops before kseg0, ckseg0 memref
- *
- * For the IDT R4000, some hazards are:
- * mtc0/mfc0 one integer op before and after
- * tlbp -- one integer op afterwards
- * Obvious solution is to take least common denominator.
- *
- * For the Toshiba R5900, TX79:
- * mtc0 following sync.p
- * tlbw[ri], tlbp following sync.p or eret
- * for those CPU, define COP0_SYNC as sync.p
- */
-
- .set noreorder
- .set mips64
-
- .text
-
-/*--------------------------------------------------------------------------
- *
- * mipsN_TLBRead --
- *
- * Read the TLB entry.
- *
- * mips3_TLBRead(entry, tlb)
- * unsigned entry;
- * struct tlb *tlb;
- *
- * Results:
- * None.
- *
- * Side effects:
- * tlb will contain the TLB entry found.
- *
- *--------------------------------------------------------------------------
- */
-LEAF(MIPSX(TLBRead))
- mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
- mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
- COP0_SYNC
- nop
- mfc0 ta2, MIPS_COP_0_TLB_PG_MASK # save current pgMask
- nop
- _MFC0 t0, MIPS_COP_0_TLB_HI # Get current PID
-
- mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index register
- COP0_SYNC
- nop
- nop # required for QED5230
- tlbr # Read from the TLB
- COP0_SYNC
- nop
- nop
- nop
- mfc0 t2, MIPS_COP_0_TLB_PG_MASK # fetch the pgMask
- _MFC0 t3, MIPS_COP_0_TLB_HI # fetch the hi entry
- _MFC0 ta0, MIPS_COP_0_TLB_LO0 # See what we got
- _MFC0 ta1, MIPS_COP_0_TLB_LO1 # See what we got
- _MTC0 t0, MIPS_COP_0_TLB_HI # restore PID
- COP0_SYNC
- mtc0 ta2, MIPS_COP_0_TLB_PG_MASK # restore pgMask
- COP0_SYNC
- nop
- nop
- nop # wait for PID active
- mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
- COP0_SYNC
- nop
- sd t2, 0(a1) # Store PageMask
- sd t3, 8(a1) # Store EntryHi
- sd ta0, 16(a1) # Store EntryLo0
- j ra # Stand there where you are
- sd ta1, 24(a1) # Store EntryLo1
-END(MIPSX(TLBRead))
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