PERFORCE change 41126 for review
Juli Mallett
jmallett at FreeBSD.org
Sun Nov 2 11:44:36 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=41126
Change 41126 by jmallett at jmallett_dalek on 2003/11/02 11:44:11
Fun with TLB invalidate.
Affected files ...
.. //depot/projects/mips/sys/mips/include/cpufunc.h#14 edit
.. //depot/projects/mips/sys/mips/include/locore.h#12 edit
.. //depot/projects/mips/sys/mips/include/tlb.h#3 edit
.. //depot/projects/mips/sys/mips/mips/machdep.c#36 edit
.. //depot/projects/mips/sys/mips/mips/mips_subr.S#17 edit
.. //depot/projects/mips/sys/mips/mips/pmap.c#20 edit
.. //depot/projects/mips/sys/mips/mips/tlb.c#9 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/cpufunc.h#14 (text+ko) ====
@@ -86,6 +86,7 @@
MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0)
MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1)
MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI)
+MIPS_RDRW64_COP0(index, MIPS_COP_0_TLB_INDEX)
MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK)
#undef MIPS_RDRW64_COP0
==== //depot/projects/mips/sys/mips/include/locore.h#12 (text+ko) ====
@@ -31,8 +31,6 @@
struct tlb;
-void mips64_TBIA(int);
-void mips64_TBIAP(int);
void mips64_TLBRead(int, struct tlb *);
void mips64_wbflush(void);
@@ -41,9 +39,6 @@
uint32_t mipsNN_cp0_config2_read(void);
uint32_t mipsNN_cp0_config3_read(void);
-#define MIPS_TBIA() mips64_TBIA(mips_num_tlb_entries)
-#define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries)
-
/*
* CPU identification, from PRID register.
*/
==== //depot/projects/mips/sys/mips/include/tlb.h#3 (text+ko) ====
@@ -20,6 +20,8 @@
void tlb_bootstrap(vm_size_t, vm_offset_t (*)(vm_size_t));
void tlb_enter(pmap_t, vm_offset_t, vm_paddr_t, pt_entry_t);
+void tlb_invalidate_all(void);
+void tlb_invalidate_one(int);
void tlb_invalidate_page(vm_offset_t);
void tlb_modified(void *);
void tlb_remove(pmap_t, vm_offset_t);
==== //depot/projects/mips/sys/mips/mips/machdep.c#36 (text+ko) ====
@@ -173,6 +173,7 @@
#include <machine/md_var.h>
#include <machine/mipsNN.h>
#include <machine/pte.h>
+#include <machine/tlb.h>
#ifdef DDB
#include <ddb/ddb.h>
@@ -730,7 +731,7 @@
case CPU_ARCH_MIPS3:
case CPU_ARCH_MIPS64:
mips_wr_wired(0);
- mips64_TBIA(mips_num_tlb_entries);
+ tlb_invalidate_all();
mips_wr_wired(MIPS3_TLB_WIRED_UPAGES);
mips64_vector_init();
break;
==== //depot/projects/mips/sys/mips/mips/mips_subr.S#17 (text+ko) ====
@@ -232,115 +232,3 @@
j ra # Stand there where you are
sd ta1, 24(a1) # Store EntryLo1
END(MIPSX(TLBRead))
-
-/*
- * void mips3_TBIAP(int sizeofTLB)
- *
- * Invalidate TLB entries belong to per process user spaces while
- * leaving entries for kernel space marked global intact.
- */
-LEAF_NOPROFILE(MIPSX(TBIAP))
- mfc0 v1, MIPS_COP_0_STATUS # save status register
- mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
- COP0_SYNC
-
- move t2, a0
- mfc0 t1, MIPS_COP_0_TLB_WIRED
- li v0, MIPS_KSEG0_START # invalid address
- mfc0 t3, MIPS_COP_0_TLB_PG_MASK # save current pgMask
-
- /* do {} while (t1 < t2) */
-1:
- mtc0 t1, MIPS_COP_0_TLB_INDEX # set index
- COP0_SYNC
- sll ta0, t1, 13 # PAGE_SHIFT + 1
- nop
- /* XXX simonb: lose this nop for mips32/64? */
- nop
- tlbr # obtain an entry
- COP0_SYNC
- /* XXX simonb: lose these nops for mips32/64? */
- nop
- nop
- nop
- _MFC0 a0, MIPS_COP_0_TLB_LO1
- and a0, a0, PG_G # check to see it has G bit
- bnez a0, 2f
- addu ta0, ta0, v0
-
- _MTC0 ta0, MIPS_COP_0_TLB_HI # make entryHi invalid
- COP0_SYNC
- _MTC0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
- COP0_SYNC
- _MTC0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
- COP0_SYNC
- mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out mask entry
- COP0_SYNC
- /* XXX simonb: lose these nops for mips32/64? */
- nop
- nop
- tlbwi # invalidate the TLB entry
- COP0_SYNC
-2:
- addu t1, t1, 1
- bne t1, t2, 1b
- nop
-
- mtc0 t3, MIPS_COP_0_TLB_PG_MASK # restore pgMask
- COP0_SYNC
- /* XXX simonb: lose these nops for mips32/64? */
- nop
- nop
- j ra # new ASID will be set soon
- mtc0 v1, MIPS_COP_0_STATUS # restore status register
- COP0_SYNC # XXXX - not executed!!
-END(MIPSX(TBIAP))
-
-/*
- * void mipsN_TBIA(int sizeofTLB)
- *
- * Invalidate all of non-wired TLB entries.
- */
-LEAF_NOPROFILE(MIPSX(TBIA))
- mfc0 v1, MIPS_COP_0_STATUS # save status register
- mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
- COP0_SYNC
-
- li v0, MIPS_KSEG0_START # invalid address
- _MFC0 t0, MIPS_COP_0_TLB_HI # save current ASID
- mfc0 t1, MIPS_COP_0_TLB_WIRED
- mfc0 t2, MIPS_COP_0_TLB_PG_MASK # save current pgMask
-
- _MTC0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
- COP0_SYNC
- _MTC0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
- COP0_SYNC
- mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask
- COP0_SYNC
-
- /* do {} while (t1 < a0) */
-1:
- mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLBindex
- COP0_SYNC
- sll ta0, t1, 13 # PAGE_SHIFT + 1
- add ta0, v0, ta0
- _MTC0 ta0, MIPS_COP_0_TLB_HI # make entryHi invalid
- COP0_SYNC
- nop
- nop
- tlbwi # clear the entry
- COP0_SYNC
- addu t1, t1, 1 # increment index
- bne t1, a0, 1b
- nop
-
- _MTC0 t0, MIPS_COP_0_TLB_HI # restore ASID
- COP0_SYNC
- mtc0 t2, MIPS_COP_0_TLB_PG_MASK # restore pgMask
- COP0_SYNC
- nop
- nop
- j ra
- mtc0 v1, MIPS_COP_0_STATUS # restore status register
- COP0_SYNC # XXXX - not executed!!
-END(MIPSX(TBIA))
==== //depot/projects/mips/sys/mips/mips/pmap.c#20 (text+ko) ====
@@ -462,7 +462,7 @@
pmap_invalidate_all(pmap_t pmap)
{
if (pmap->pm_active) {
- MIPS_TBIAP();
+ tlb_invalidate_all();
/* XXX ensure coherency? */
} else
pmap_invalidate_asid(pmap);
@@ -507,7 +507,7 @@
* clear out the TLB and the I-cache since they are tagged
* with the ASID.
*/
- MIPS_TBIAP();
+ tlb_invalidate_all();
/* XXX flush icache. */
}
pmap->pm_asid = PCPU_GET(next_asid);
==== //depot/projects/mips/sys/mips/mips/tlb.c#9 (text+ko) ====
@@ -92,7 +92,7 @@
* Initialise ASID and clear TLB.
*/
mips_wr_entryhi(0);
- MIPS_TBIA();
+ tlb_invalidate_all();
}
void
@@ -159,12 +159,34 @@
}
void
+tlb_invalidate_all(void)
+{
+ u_long asid;
+ int i;
+
+ asid = mips_rd_entryhi();
+ for (i = 0; i < mips_num_tlb_entries; i++)
+ tlb_invalidate_one(i);
+ mips_wr_entryhi(asid);
+}
+
+void
+tlb_invalidate_one(int i)
+{
+ u_long ehi;
+
+ /* Bogus VPN2. */
+ ehi = MIPS_XKSEG_START + 2 * i * PAGE_SIZE;
+ mips_wr_index(i);
+ mips_wr_entryhi(ehi);
+ mips_tlbwi();
+}
+
+void
tlb_invalidate_page(vm_offset_t va)
{
va &= ~PAGE_MASK;
-#if 1 /* XXX NetBSD code is faulty. Invalidate ALL. */
- MIPS_TBIA();
-#endif
+ tlb_invalidate_all();
}
void
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