PERFORCE change 32458 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=32458

Change 32458 by jmallett at jmallett_dalek on 2003/06/02 22:36:34

	Update for new PTE header & C99.

Affected files ...

.. //depot/projects/mips/sys/mips/mips/mips_subr.S#8 edit

Differences ...

==== //depot/projects/mips/sys/mips/mips/mips_subr.S#8 (text+ko) ====

@@ -226,13 +226,13 @@
 	mfc0	v1, MIPS_COP_0_STATUS	# Save the status register.
 	mtc0	zero, MIPS_COP_0_STATUS	# Disable interrupts
 	COP0_SYNC
-	and	t1, a0, MIPS3_PG_ODDPG	# t1 = Even/Odd flag
-	li	v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
+	and	t1, a0, PG_ODDPG	# t1 = Even/Odd flag
+	li	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# Save current PID
 	_MTC0	a0, MIPS_COP_0_TLB_HI		# Init high reg
 	COP0_SYNC
-	and	a2, a1, MIPS3_PG_G		# Copy global bit
+	and	a2, a1, PG_G			# Copy global bit
 	nop
 	nop
 	tlbp					# Probe for the entry.
@@ -241,7 +241,7 @@
 	_SRL	a1, a1, WIRED_SHIFT
 	bne	t1, zero, 2f			# Decide even odd
 	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
-# EVEN
+/* EVEN */
 	nop
 	bltz	v0, 1f				# index < 0 => !found
 	nop
@@ -284,7 +284,7 @@
 	nop					# required for QED5230
 	b	4f
 	nop
-# ODD
+/* ODD */
 2:
 	nop
 	bltz	v0, 3f				# index < 0 => !found
@@ -388,11 +388,11 @@
 	mtc0	v1, MIPS_COP_0_STATUS		# Restore the status register
 	COP0_SYNC
 	nop
-	sw	t2, 0(a1)
-	sw	t3, 4(a1)
-	sw	ta0, 8(a1)
-	j	ra
-	sw	ta1, 12(a1)
+	sd	t2, 0(a1)			# Store PageMask
+	sd	t3, 8(a1)			# Store EntryHi
+	sd	ta0, 16(a1)			# Store EntryLo0
+	j	ra				# Stand there where you are
+	sd	ta1, 24(a1)			# Store EntryLo1
 END(MIPSX(TLBRead))
 
 /*
@@ -407,12 +407,12 @@
 	jal	ra, s0
 	move	a0, s1
 	.set	noat
-	#
-	# Make sure to disable interrupts here, as otherwise
-	# we can take an interrupt *after* EXL is set, and
-	# end up returning to a bogus PC since the PC is not
-	# saved if EXL=1.
-	#
+	/*
+	 * Make sure to disable interrupts here, as otherwise
+	 * we can take an interrupt *after* EXL is set, and
+	 * end up returning to a bogus PC since the PC is not
+	 * saved if EXL=1.
+	 */
 	mtc0	zero, MIPS_COP_0_STATUS		# disable int
 	COP0_SYNC
 	nop					# 3 op delay
@@ -424,7 +424,7 @@
 	nop
 	nop
 	addu	a1, sp, CALLFRAME_SIZ
- #	REG_L	a0, FRAME_SR(a1)
+ /*	REG_L	a0, FRAME_SR(a1) */
 	REG_L	t0, FRAME_MULLO(a1)
 	REG_L	t1, FRAME_MULHI(a1)
 	REG_L	v0, FRAME_EPC(a1)
@@ -497,7 +497,7 @@
 	blt	v0, s0, resume
 	nop
 
-	and	s0, v0, MIPS3_PG_ODDPG
+	and	s0, v0, PG_ODDPG
 	beq	s0, zero, entry0
 	nop
 
@@ -534,10 +534,10 @@
 entry0set:
 	mtc0	zero, MIPS_COP_0_TLB_INDEX	# TLB entry #0
 	COP0_SYNC
-	or	a1, MIPS3_PG_G
+	or	a1, PG_G
 	_MTC0	a1, MIPS_COP_0_TLB_LO0		# upte[0] | PG_G
 	COP0_SYNC
-	or	a2, MIPS3_PG_G
+	or	a2, PG_G
 	_MTC0	a2, MIPS_COP_0_TLB_LO1		# upte[1] | PG_G
 	COP0_SYNC
 	nop
@@ -562,7 +562,7 @@
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 	COP0_SYNC
 
-	li	v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
+	li	v0, (PG_HVPN | PG_ASID)
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# save current ASID
 	mfc0	t3, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
 	and	a0, a0, v0			# make sure valid entryHi
@@ -575,8 +575,8 @@
 	nop
 	nop
 	mfc0	v0, MIPS_COP_0_TLB_INDEX	# see what we got
-	#nop					# -slip-
-	#nop					# -slip-
+	/*nop					# -slip-*/
+	/*nop					# -slip-*/
 	bltz	v0, 1f				# index < 0 then skip
 	li	t1, MIPS_KSEG0_START		# invalid address
 	sll	v0, v0, 13			# PAGE_SHIFT + 1
@@ -623,7 +623,7 @@
 	li	v0, MIPS_KSEG0_START		# invalid address
 	mfc0	t3, MIPS_COP_0_TLB_PG_MASK	# save current pgMask
 
-	# do {} while (t1 < t2)
+	/* do {} while (t1 < t2) */
 1:
 	mtc0	t1, MIPS_COP_0_TLB_INDEX	# set index
 	COP0_SYNC
@@ -638,7 +638,7 @@
 	nop
 	nop
 	_MFC0	a0, MIPS_COP_0_TLB_LO1
-	and	a0, a0, MIPS3_PG_G		# check to see it has G bit
+	and	a0, a0, PG_G			# check to see it has G bit
 	bnez	a0, 2f
 	addu	ta0, ta0, v0
 
@@ -692,7 +692,7 @@
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out pageMask
 	COP0_SYNC
 
-	# do {} while (t1 < a0)
+	/* do {} while (t1 < a0) */
 1:
 	mtc0	t1, MIPS_COP_0_TLB_INDEX	# set TLBindex
 	COP0_SYNC