PERFORCE change 44334 for review
Juli Mallett
jmallett at FreeBSD.org
Thu Dec 25 18:56:33 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=44334
Change 44334 by jmallett at jmallett_oingo on 2003/12/25 18:55:59
Remove redundant indirections, etc.
Affected files ...
.. //depot/projects/mips/sys/mips/include/asm.h#12 edit
.. //depot/projects/mips/sys/mips/mips/cache_r4k.c#2 edit
.. //depot/projects/mips/sys/mips/mips/locore_mips3.S#14 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/asm.h#12 (text+ko) ====
@@ -135,29 +135,4 @@
9: .asciiz msg; \
.text
-/*
- * standard callframe {
- * register_t cf_args[4]; arg0 - arg3
- * register_t cf_sp; frame pointer
- * register_t cf_ra; return address
- * };
- */
-#define CALLFRAME_SIZ (8 * (4 + 2))
-#define CALLFRAME_SP (8 * 4)
-#define CALLFRAME_RA (8 * 5)
-
-/*
- * While it would be nice to be compatible with the SGI
- * REG_L and REG_S macros, because they do not take parameters, it
- * is impossible to use them with the _MIPS_SIM_ABIX32 model.
- *
- * These macros hide the use of mips3 instructions from the
- * assembler to prevent the assembler from generating 64-bit style
- * ABI calls.
- */
-#define REG_L ld
-#define REG_S sd
-#define REG_LI dli
-#define SZREG 8
-
#endif /* !_MACHINE_ASM_H_ */
==== //depot/projects/mips/sys/mips/mips/cache_r4k.c#2 (text+ko) ====
@@ -57,8 +57,6 @@
#define round_line(x) (((x) + 15) & ~15)
#define trunc_line(x) ((x) & ~15)
-__asm(".set mips3");
-
void
r4k_icache_sync_all_16(void)
{
==== //depot/projects/mips/sys/mips/mips/locore_mips3.S#14 (text+ko) ====
@@ -187,35 +187,35 @@
*/
LEAF(setjmp)
mfc0 v0, MIPS_COP_0_STATUS
- REG_S s0, SF_REG_S0(a0)
- REG_S s1, SF_REG_S1(a0)
- REG_S s2, SF_REG_S2(a0)
- REG_S s3, SF_REG_S3(a0)
- REG_S s4, SF_REG_S4(a0)
- REG_S s5, SF_REG_S5(a0)
- REG_S s6, SF_REG_S6(a0)
- REG_S s7, SF_REG_S7(a0)
- REG_S sp, SF_REG_SP(a0)
- REG_S s8, SF_REG_S8(a0)
- REG_S ra, SF_REG_RA(a0)
- REG_S v0, SF_REG_SR(a0)
+ sd s0, SF_REG_S0(a0)
+ sd s1, SF_REG_S1(a0)
+ sd s2, SF_REG_S2(a0)
+ sd s3, SF_REG_S3(a0)
+ sd s4, SF_REG_S4(a0)
+ sd s5, SF_REG_S5(a0)
+ sd s6, SF_REG_S6(a0)
+ sd s7, SF_REG_S7(a0)
+ sd sp, SF_REG_SP(a0)
+ sd s8, SF_REG_S8(a0)
+ sd ra, SF_REG_RA(a0)
+ sd v0, SF_REG_SR(a0)
j ra
move v0, zero
END(setjmp)
LEAF(longjmp)
- REG_L v0, SF_REG_SR(a0)
- REG_L ra, SF_REG_RA(a0)
- REG_L s0, SF_REG_S0(a0)
- REG_L s1, SF_REG_S1(a0)
- REG_L s2, SF_REG_S2(a0)
- REG_L s3, SF_REG_S3(a0)
- REG_L s4, SF_REG_S4(a0)
- REG_L s5, SF_REG_S5(a0)
- REG_L s6, SF_REG_S6(a0)
- REG_L s7, SF_REG_S7(a0)
- REG_L sp, SF_REG_SP(a0)
- REG_L s8, SF_REG_S8(a0)
+ ld v0, SF_REG_SR(a0)
+ ld ra, SF_REG_RA(a0)
+ ld s0, SF_REG_S0(a0)
+ ld s1, SF_REG_S1(a0)
+ ld s2, SF_REG_S2(a0)
+ ld s3, SF_REG_S3(a0)
+ ld s4, SF_REG_S4(a0)
+ ld s5, SF_REG_S5(a0)
+ ld s6, SF_REG_S6(a0)
+ ld s7, SF_REG_S7(a0)
+ ld sp, SF_REG_SP(a0)
+ ld s8, SF_REG_S8(a0)
mtc0 v0, MIPS_COP_0_STATUS
COP0_SYNC
j ra
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