PERFORCE change 29638 for review
Marcel Moolenaar
marcel at FreeBSD.org
Thu Apr 24 15:02:37 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=29638
Change 29638 by marcel at marcel_nfs on 2003/04/24 15:02:03
Improve exception handling:
o Stop getting the faulting address directly from cr.ifa. There
are faults/traps that set cr.iim. Instead of copying cr.iim
to cr.ifa before constructing the trapframe, we now pass the
value for cr.ifa as an argument to the code that constructs
the trapframe. The added upside is that we don't need to save
and restore cr.ifa when we get a data nested TLB. This removes
a couple of serializations. For external interrupts we pass
the processor APIC ID as the value to store in the trapframe.
Both cr.ifa and cr.iim are undefined in that case and we might
as well put something potential useful there.
o Don't use a translation register when inserting a mapping on
a data nested TLB. The problem with a translation register is
that we don't keep it in sync with data structures in the
kernel. This can lead to using faulty translations. The problem
I was trying to solve by using a translation register is one
that didn't exist. See next bullet.
o We can get 2 distinct TLB misses when restoring from a trapframe.
The first is the very first load out of the trapframe itself.
This one we don't care about. It will be handled like any other
TLB miss. The second one was the one I didn't see and that the
possible TLB miss on the loadrs instruction. The register stack
does not have to be mapped currently and since the loadrs is
a mandatory RSE operation, faults will occur. The problem here
is that most of the context has already been restored, so we
can not treat it as a regular miss. Hence, we force a data
nested TLB by disabling interrupt collection. Of course, now
that we have 2 places where we expect data nested TLB faults,
we need to sync register usage between those two places and
the data nested TLB fault handler. This involves a lot of manual
register re-allocation :-(
This solves the sporadic machine checks and hangs I was getting
and slightly improves the overall handling of exceptions.
Affected files ...
.. //depot/projects/ia64_epc/sys/ia64/ia64/exception.s#17 edit
Differences ...
==== //depot/projects/ia64_epc/sys/ia64/ia64/exception.s#17 (text+ko) ====
@@ -1,4 +1,5 @@
/*-
+ * Copyright (c) 2003 Marcel Moolenaar
* Copyright (c) 2000 Doug Rabson
* All rights reserved.
*
@@ -45,6 +46,10 @@
* Arguments:
* r16 address of bundle that contains the branch. The
* return address will be the next bundle.
+ * r17 the value to save as ifa in the trapframe. This
+ * normally is cr.ifa, but some interruptions set
+ * set cr.iim and not cr.ifa.
+ *
* Returns:
* p15 interrupted from user stack
* p14 interrupted from kernel stack
@@ -55,36 +60,34 @@
*/
ENTRY(exception_save, 0)
{ .mii
- mov r17=sp
+ mov r20=ar.unat
+ extr.u r31=sp,61,3
mov r18=pr
- extr.u r31=sp,61,3
;;
}
{ .mmi
cmp.le p14,p15=5,r31
;;
-(p15) mov r31=ar.k7 // kernel memory stack
-(p14) mov r31=sp
+(p15) mov r23=ar.k7 // kernel memory stack
+(p14) mov r23=sp
;;
}
-{ .mmi
- add r30=-SIZEOF_TRAPFRAME,r31
+{ .mii
+ mov r21=ar.rsc
+ add r30=-SIZEOF_TRAPFRAME,r23
;;
- mov r20=ar.unat
- dep sp=0,r30,0,10
+ dep r30=0,r30,0,10
;;
}
{ .mmi
- mov r21=ar.rsc
mov ar.rsc=0
- sub r19=r31,sp
+ sub r19=r23,r30
+ add r31=8,r30
;;
}
-{ .mmi
- rsm psr.i
- ;;
- srlz.d
- mov r22=ip
+{ .mlx
+ mov r22=cr.iip
+ movl r26=exception_save_restart
;;
}
@@ -95,91 +98,92 @@
* we get a data nested TLB fault, it will be on the very first
* write. Since the data nested TLB fault does not preserve any
* state, we have to be careful what we clobber. Consequently, we
- * have to be careful what we use here. The registers that must
- * not be clobbered by the data nested TLB fault handler on top
- * of any interrupted state we haven't saved yet (ie almost all
- * of it) are: p14, p15, sp and r16-r22.
+ * have to be careful what we use here. Below a list of registers
+ * that are currently alive:
+ * r16,r17=arguments
+ * r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
+ * r26=restart point
+ * r30,r31=trapframe pointers
+ * p14,p15=memory stack switch
*/
exception_save_restart:
{ .mmi
- st8 [sp]=r19 // length
- mov r22=cr.iip
- add r31=8,sp
+ st8 [r30]=r19,16 // length
+ st8 [r31]=r0,16 // flags
+ add r19=16,r19
;;
}
{ .mmi
- st8 [r31]=r0,16 // flags
- mov r29=ar.bspstore
- add r30=16,sp
+ st8.spill [r30]=sp,16 // sp
+ st8 [r31]=r20,16 // unat
+ sub sp=r23,r19
;;
}
{ .mmi
- st8.spill [r30]=r17,16 // sp
- st8 [r31]=r20,16 // unat
- mov r27=b0
+ mov r19=ar.rnat
+ mov r20=ar.bspstore
+ mov r23=rp
;;
}
+ // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp
{ .mmi
- st8 [r30]=r27,16 // rp
+ st8 [r30]=r23,16 // rp
st8 [r31]=r18,16 // pr
- mov r27=ar.pfs
+ mov r24=ar.pfs
;;
}
{ .mmb
- st8 [r30]=r27,16 // pfs
- st8 [r31]=r29,16 // bspstore
+ st8 [r30]=r24,16 // pfs
+ st8 [r31]=r20,16 // bspstore
cover
;;
}
{ .mmi
- mov r17=ar.rnat
mov r18=ar.fpsr
- extr.u r28=r29,61,3
+ mov r23=cr.ipsr
+ extr.u r24=r20,61,3
;;
}
+ // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr
{ .mmi
- st8 [r30]=r17,16 // rnat
+ st8 [r30]=r19,16 // rnat
st8 [r31]=r0,16 // __spare
- cmp.le p12,p13=5,r28
+ cmp.le p12,p13=5,r24
;;
}
{ .mmi
st8.spill [r30]=r13,16 // tp
st8 [r31]=r21,16 // rsc
- nop 0
+ tbit.nz p11,p10=r23,14 // p11=interrupts enabled
;;
}
{ .mmi
- mov r17=cr.ipsr
-(p13) mov r29=ar.k6 // kernel register stack
+ st8 [r30]=r18,16 // fpsr
+(p13) mov r20=ar.k6 // kernel register stack
nop 0
;;
}
+ // r20=bspstore, r22=iip, r23=ipsr
{ .mmi
- st8 [r30]=r18,16 // fpsr
- st8 [r31]=r17,16 // psr
- tbit.nz p11,p10=r17,14 // p11=interrupts enabled
+ st8 [r31]=r23,16 // psr
+ mov ar.bspstore=r20
+ nop 0
;;
}
{ .mmi
- mov ar.bspstore=r29
- ;;
mov r18=ar.bsp
- nop 0
;;
-}
-{ .mmi
- st8.spill [r30]=gp,16 // gp
mov r19=cr.ifs
- sub r18=r18,r29
+ sub r18=r18,r20
;;
}
{ .mmi
+ st8.spill [r30]=gp,16 // gp
st8 [r31]=r18,16 // ndirty
- mov r20=cr.ifa
nop 0
;;
}
+ // r19=ifs, r22=iip
{ .mmi
st8 [r30]=r19,16 // cfm
st8 [r31]=r22,16 // iip
@@ -187,7 +191,7 @@
;;
}
{ .mmi
- st8 [r30]=r20 // ifa
+ st8 [r30]=r17 // ifa
mov r18=cr.isr
add r29=16,r30
;;
@@ -354,17 +358,10 @@
* sp+16 trapframe pointer
*/
ENTRY(exception_restore, 0)
- /*
- * Read the length of the trapframe with interrupts enabled and
- * interrupt collection enabled. That way we can safely trap on
- * the load in case the address translation of the trapframe has
- * been flushed.
- */
{ .mmi
rsm psr.i
- ;;
- srlz.d
add sp=16,sp
+ nop 0
;;
}
{ .mmi
@@ -373,7 +370,7 @@
add r8=SIZEOF_SPECIAL+16,sp
;;
}
-
+ // The next load can trap. Let it be...
ldf.fill f15=[r2],-32 // f15
ldf.fill f14=[r3],-32 // f14
;;
@@ -469,19 +466,26 @@
ld8.fill r3=[r3] // r3
;;
}
-
+ // We want nested TLB faults from here on...
+ rsm psr.ic|psr.i
ld8.fill r2=[r2] // r2
+ nop 0
+ ;;
+ srlz.d
ld8.fill sp=[r31],16 // sp
+ nop 0
;;
+
ld8 r17=[r30],16 // unat
ld8 r29=[r31],16 // rp
;;
ld8 r18=[r30],16 // pr
- ld8 r19=[r31],16 // pfs
+ ld8 r28=[r31],16 // pfs
mov rp=r29
;;
ld8 r20=[r30],24 // bspstore
ld8 r21=[r31],24 // rnat
+ mov ar.pfs=r28
;;
ld8.fill r29=[r30],16 // tp
ld8 r22=[r31],16 // rsc
@@ -500,19 +504,31 @@
}
{ .mmb
ld8 r26=[r30] // cfm
- ld8 r27=[r31] // ip
+ ld8 r19=[r31] // ip
(p14) br.cond.sptk 1f
;;
}
{ .mii
// Switch register stack
- alloc r31=ar.pfs,0,0,0,0 // discard current frame
- shl r30=r25,16 // value for ar.rsc
+ alloc r30=ar.pfs,0,0,0,0 // discard current frame
+ shl r31=r25,16 // value for ar.rsc
dep r24=-1,r24,19,1 // XXX disable high FP.
;;
}
+ // The loadrs can fault if the backing store is not currently
+ // mapped. We assured forward progress by getting everything we
+ // need from the trapframe so that we don't care if the CPU
+ // purges that translation when it needs to insert a new one for
+ // the backing store.
{ .mmi
- mov ar.rsc=r30 // setup for loadrs
+ mov ar.rsc=r31 // setup for loadrs
+ mov ar.k7=r16
+ mov r13=r29
+ ;;
+}
+exception_restore_restart:
+{ .mmi
+ mov r30=ar.bspstore
;;
loadrs // load user regs
nop 0
@@ -525,27 +541,19 @@
dep r31=0,r31,0,9
;;
}
-
+{ .mmb
mov ar.k6=r31
- mov ar.k7=r16
- ;;
mov ar.rnat=r21
- mov r13=r29
+ nop 0
;;
-
+}
1:
-{ .mmi
- rsm psr.ic
- ;;
- srlz.d
+{ .mmb
+ mov ar.unat=r17
+ mov cr.iip=r19
nop 0
}
{ .mmi
- mov ar.unat=r17
- mov cr.iip=r27
- mov ar.pfs=r19
-}
-{ .mmi
mov cr.ipsr=r24
mov cr.ifs=r26
mov pr=r18,0x1fffe
@@ -568,9 +576,9 @@
* which will restore the interrupted state before executing an rfi to
* resume it.
*/
-#define TRAP(_n_) \
+#define TRAP(_n_, _ifa_) \
{ .mib ; \
- nop _n_ ; \
+ mov r17=_ifa_ ; \
mov r16=ip ; \
br.sptk exception_save ; \
} ; \
@@ -579,9 +587,9 @@
alloc r15=ar.pfs,0,0,2,0 ; \
mov out0=_n_ ;; \
} ; \
-{ .mmb ; \
- mov out1=sp ; \
- add sp=-16,sp ; \
+{ .mfb ; \
+ add out1=16,sp ; \
+ nop 0 ; \
br.call.sptk rp=trap ; \
} ; \
{ .mfb ; \
@@ -617,7 +625,7 @@
ia64_vector_table:
IVT_ENTRY(VHPT_Translation, 0x0000)
- TRAP(0)
+ TRAP(0, cr.ifa)
IVT_END(VHPT_Translation)
IVT_ENTRY(Instruction_TLB, 0x0400)
@@ -694,7 +702,7 @@
;;
srlz.d
;;
- TRAP(20) // Page Not Present trap
+ TRAP(20, cr.ifa) // Page Not Present trap
IVT_END(Instruction_TLB)
IVT_ENTRY(Data_TLB, 0x0800)
@@ -771,7 +779,7 @@
;;
srlz.d
;;
- TRAP(20) // Page Not Present trap
+ TRAP(20, cr.ifa) // Page Not Present trap
IVT_END(Data_TLB)
IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00)
@@ -796,7 +804,7 @@
;;
rfi
9: mov pr=r18,0x1ffff // restore predicates
- TRAP(3)
+ TRAP(3, cr.ifa)
IVT_END(Alternate_Instruction_TLB)
IVT_ENTRY(Alternate_Data_TLB, 0x1000)
@@ -821,101 +829,92 @@
;;
rfi
9: mov pr=r18,0x1ffff // restore predicates
- TRAP(4)
+ TRAP(4, cr.ifa)
IVT_END(Alternate_Data_TLB)
IVT_ENTRY(Data_Nested_TLB, 0x1400)
- // See exception_save. Things get tricky here. Don't use p14, p15,
- // sp and r16-r22. We use physical addressing to avoid double
- // nested faults. Since all virtual addresses we encounter here
- // are direct mapped region 7 addresses, we will have no problem
+ // See exception_save_restart and exception_restore_restart for the
+ // contexts that may cause a data nested TLB. We can only use the
+ // banked general registers and predicates, but don't use:
+ // p14 & p15 - Set in exception save
+ // r16 & r17 - Arguments to exception save
+ // r30 - Faulting address (modulo page size)
+ // We assume r30 has the virtual addresses that relate to the data
+ // nested TLB fault. The address does not have to be exact, as long
+ // as it's in the same page. We use physical addressing to avoid
+ // double nested faults. Since all virtual addresses we encounter
+ // here are direct mapped region 7 addresses, we have no problem
// constructing physical addresses.
{ .mlx
- mov r23=cr.ifa
- movl r25=ia64_kptdir
+ rsm psr.dt
+ movl r27=ia64_kptdir
;;
}
{ .mii
- mov r24=cr.itir
- dep r25=0,r25,61,3
- extr.u r26=sp,PAGE_SHIFT,61-PAGE_SHIFT
+ srlz.d
+ dep r27=0,r27,61,3
+ extr.u r28=r30,PAGE_SHIFT,61-PAGE_SHIFT
;;
}
{ .mii
- rsm psr.dt
- shr.u r27=r26,PAGE_SHIFT-5 // dir index
- extr.u r28=r26,0,PAGE_SHIFT-5 // pte index
+ ld8 r27=[r27]
+ shr.u r29=r28,PAGE_SHIFT-5 // dir index
+ extr.u r28=r28,0,PAGE_SHIFT-5 // pte index
;;
}
{ .mmi
- srlz.d
- ld8 r25=[r25]
- shl r28=r28,5
+ shladd r27=r29,3,r27
+ ;;
+ mov cr.ifa=r30
+ dep r27=0,r27,61,3
;;
}
{ .mmi
- mov cr.ifa=sp
- shladd r25=r27,3,r25
- add r22=16,r22
+ ld8 r27=[r27]
+ mov r29=rr[r30]
+ shl r28=r28,5
;;
}
{ .mii
- mov r27=rr[sp]
- dep r25=0,r25,61,3
+ add r27=r27,r28 // address of pte
+ dep r29=0,r29,0,2
;;
- dep r27=0,r27,0,2
-}
-{ .mlx
- ld8 r25=[r25]
- movl r29=exception_save_restart
+ dep r27=0,r27,61,3
;;
}
-{ .mii
- mov cr.itir=r27
- add r25=r25,r28 // address of pte
+{ .mmi
+ ld8 r28=[r27]
;;
- dep r25=0,r25,61,3
+ mov cr.itir=r29
+ or r28=PTE_D|PTE_A,r28
;;
}
-{ .mmi
- ld8 r26=[r25]
- ;;
- or r26=PTE_D|PTE_A,r26
- cmp.eq p13,p0=r22,r29 // exception_save triggered?
+{ .mlx
+ st8 [r27]=r28
+ movl r29=exception_save_restart
;;
}
{ .mmi
- st8 [r25]=r26
+ itc.d r28
;;
ssm psr.dt
- mov r28=4
+ cmp.eq p12,p13=r26,r29
+ ;;
}
-{ .mmi
- itr.d dtr[r28]=r26
- ;;
+{ .mbb
srlz.d
- nop 0
-}
-{ .mmb
- mov cr.ifa=r23
- mov cr.itir=r24
-(p13) br.sptk exception_save_restart
- ;;
-}
-{ .mfb
- break 0x80100
- break 0x80100
- break 0x80100
+(p12) br.sptk exception_save_restart
+(p13) br.sptk exception_restore_restart
;;
}
IVT_END(Data_Nested_TLB)
IVT_ENTRY(Instruction_Key_Miss, 0x1800)
- TRAP(6)
+ TRAP(6, cr.ifa)
IVT_END(Instruction_Key_Miss)
IVT_ENTRY(Data_Key_Miss, 0x1c00)
- TRAP(7)
+ TRAP(7, cr.ifa)
IVT_END(Data_Key_Miss)
IVT_ENTRY(Dirty_Bit, 0x2000)
@@ -984,7 +983,7 @@
br.cond.sptk.few 1b // loop
9: mov pr=r17,0x1ffff // restore predicates
- TRAP(8) // die horribly
+ TRAP(8, cr.ifa) // die horribly
IVT_END(Dirty_Bit)
IVT_ENTRY(Instruction_Access_Bit, 0x2400)
@@ -1053,7 +1052,7 @@
br.cond.sptk.few 1b // loop
9: mov pr=r17,0x1ffff // restore predicates
- TRAP(9)
+ TRAP(9, cr.ifa)
IVT_END(Instruction_Access_Bit)
IVT_ENTRY(Data_Access_Bit, 0x2800)
@@ -1122,38 +1121,25 @@
br.cond.sptk.few 1b // loop
9: mov pr=r17,0x1ffff // restore predicates
- TRAP(10)
+ TRAP(10, cr.ifa)
IVT_END(Data_Access_Bit)
IVT_ENTRY(Break_Instruction, 0x2c00)
-{ .mmi
- mov r16=cr.iim
- ;;
- mov cr.ifa=r16
- nop 0
- ;;
-}
{ .mib
- srlz.d
+ mov r17=cr.iim
mov r16=ip
br.sptk exception_save
;;
}
{ .mmi
+ alloc r15=ar.pfs,0,0,2,0
flushrs
-(p11) ssm psr.i
- nop 0
- ;;
-}
-{ .mmi
- alloc r15=ar.pfs,0,0,2,0
mov out0=11
- mov out1=sp
;;
}
-{ .mfb
- add sp=-16,sp
- nop 0
+{ .mib
+(p11) ssm psr.i
+ add out1=16,sp
br.call.sptk rp=trap
;;
}
@@ -1167,15 +1153,15 @@
IVT_ENTRY(External_Interrupt, 0x3000)
{ .mib
- nop 12
+ mov r17=cr.lid // cr.iim and cr.ifa are undefined.
mov r16=ip
br.sptk exception_save
;;
}
-{ .mmi
+{ .mmb
2: alloc r14=ar.pfs,0,0,2,0 // make a frame for calling with
- mov out1=sp
- add sp=-16,sp
+ add out1=16,sp
+ nop 0
}
3: mov out0=cr.ivr // find interrupt vector
@@ -1184,8 +1170,6 @@
(p15) br.dpnt.few exception_restore // if spurious, we are done
;;
ssm psr.i // re-enable interrupts
- ;; // now that we are in-progress
- srlz.d
br.call.sptk.many rp=interrupt // call high-level handler
;;
rsm psr.i // disable interrupts
@@ -1199,245 +1183,221 @@
IVT_END(External_Interrupt)
IVT_ENTRY(Reserved_3400, 0x3400)
- TRAP(13)
+ TRAP(13, cr.ifa)
IVT_END(Reserved_3400)
IVT_ENTRY(Reserved_3800, 0x3800)
- TRAP(14)
+ TRAP(14, cr.ifa)
IVT_END(Reserved_3800)
IVT_ENTRY(Reserved_3c00, 0x3c00)
- TRAP(15)
+ TRAP(15, cr.ifa)
IVT_END(Reserved_3c00)
IVT_ENTRY(Reserved_4000, 0x4000)
- TRAP(16)
+ TRAP(16, cr.ifa)
IVT_END(Reserved_4000)
IVT_ENTRY(Reserved_4400, 0x4400)
- TRAP(17)
+ TRAP(17, cr.ifa)
IVT_END(Reserved_4400)
IVT_ENTRY(Reserved_4800, 0x4800)
- TRAP(18)
+ TRAP(18, cr.ifa)
IVT_END(Reserved_4800)
IVT_ENTRY(Reserved_4c00, 0x4c00)
- TRAP(19)
+ TRAP(19, cr.ifa)
IVT_END(Reserved_4c00)
IVT_ENTRY(Page_Not_Present, 0x5000)
- TRAP(20)
+ TRAP(20, cr.ifa)
IVT_END(Page_Not_Present)
IVT_ENTRY(Key_Permission, 0x5100)
- TRAP(21)
+ TRAP(21, cr.ifa)
IVT_END(Key_Permission)
IVT_ENTRY(Instruction_Access_Rights, 0x5200)
- TRAP(22)
+ TRAP(22, cr.ifa)
IVT_END(Instruction_Access_Rights)
IVT_ENTRY(Data_Access_Rights, 0x5300)
- TRAP(23)
+ TRAP(23, cr.ifa)
IVT_END(Data_Access_Rights)
IVT_ENTRY(General_Exception, 0x5400)
- TRAP(24)
+ TRAP(24, cr.ifa)
IVT_END(General_Exception)
IVT_ENTRY(Disabled_FP_Register, 0x5500)
- TRAP(25)
+ TRAP(25, cr.ifa)
IVT_END(Disabled_FP_Register)
IVT_ENTRY(NaT_Consumption, 0x5600)
- TRAP(26)
+ TRAP(26, cr.ifa)
IVT_END(NaT_Consumption)
IVT_ENTRY(Speculation, 0x5700)
-{ .mmi
- mov r16=cr.iim
- ;;
- mov cr.ifa=r16
- nop 0
- ;;
-}
-{ .mfb
- srlz.d
- nop 0
- nop 0
-}
- TRAP(27)
+ TRAP(27, cr.iim)
IVT_END(Speculation)
IVT_ENTRY(Reserved_5800, 0x5800)
- TRAP(28)
+ TRAP(28, cr.ifa)
IVT_END(Reserved_5800)
IVT_ENTRY(Debug, 0x5900)
- TRAP(29)
+ TRAP(29, cr.ifa)
IVT_END(Debug)
IVT_ENTRY(Unaligned_Reference, 0x5a00)
- TRAP(30)
+ TRAP(30, cr.ifa)
IVT_END(Unaligned_Reference)
IVT_ENTRY(Unsupported_Data_Reference, 0x5b00)
- TRAP(31)
+ TRAP(31, cr.ifa)
IVT_END(Unsupported_Data_Reference)
IVT_ENTRY(Floating_Point_Fault, 0x5c00)
- TRAP(32)
+ TRAP(32, cr.ifa)
IVT_END(Floating_Point_Fault)
IVT_ENTRY(Floating_Point_Trap, 0x5d00)
- TRAP(33)
+ TRAP(33, cr.ifa)
IVT_END(Floating_Point_Trap)
IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00)
- TRAP(34)
+ TRAP(34, cr.ifa)
IVT_END(Lower_Privilege_Transfer_Trap)
IVT_ENTRY(Taken_Branch_Trap, 0x5f00)
- TRAP(35)
+ TRAP(35, cr.ifa)
IVT_END(Taken_Branch_Trap)
IVT_ENTRY(Single_Step_Trap, 0x6000)
- TRAP(36)
+ TRAP(36, cr.ifa)
IVT_END(Single_Step_Trap)
IVT_ENTRY(Reserved_6100, 0x6100)
- TRAP(37)
+ TRAP(37, cr.ifa)
IVT_END(Reserved_6100)
IVT_ENTRY(Reserved_6200, 0x6200)
- TRAP(38)
+ TRAP(38, cr.ifa)
IVT_END(Reserved_6200)
IVT_ENTRY(Reserved_6300, 0x6300)
- TRAP(39)
+ TRAP(39, cr.ifa)
IVT_END(Reserved_6300)
IVT_ENTRY(Reserved_6400, 0x6400)
- TRAP(40)
+ TRAP(40, cr.ifa)
IVT_END(Reserved_6400)
IVT_ENTRY(Reserved_6500, 0x6500)
- TRAP(41)
+ TRAP(41, cr.ifa)
IVT_END(Reserved_6500)
IVT_ENTRY(Reserved_6600, 0x6600)
- TRAP(42)
+ TRAP(42, cr.ifa)
IVT_END(Reserved_6600)
IVT_ENTRY(Reserved_6700, 0x6700)
- TRAP(43)
+ TRAP(43, cr.ifa)
IVT_END(Reserved_6700)
IVT_ENTRY(Reserved_6800, 0x6800)
- TRAP(44)
+ TRAP(44, cr.ifa)
IVT_END(Reserved_6800)
IVT_ENTRY(IA_32_Exception, 0x6900)
- TRAP(45)
+ TRAP(45, cr.ifa)
IVT_END(IA_32_Exception)
IVT_ENTRY(IA_32_Intercept, 0x6a00)
-{ .mmi
- mov r16=cr.iim
- ;;
- mov cr.ifa=r16
- nop 0
- ;;
-}
-{ .mfb
- srlz.d
- nop 0
- nop 0
-}
- TRAP(46)
+ TRAP(46, cr.iim)
IVT_END(IA_32_Intercept)
IVT_ENTRY(IA_32_Interrupt, 0x6b00)
- TRAP(47)
+ TRAP(47, cr.ifa)
IVT_END(IA_32_Interrupt)
IVT_ENTRY(Reserved_6c00, 0x6c00)
- TRAP(48)
+ TRAP(48, cr.ifa)
IVT_END(Reserved_6c00)
IVT_ENTRY(Reserved_6d00, 0x6d00)
- TRAP(49)
+ TRAP(49, cr.ifa)
IVT_END(Reserved_6d00)
IVT_ENTRY(Reserved_6e00, 0x6e00)
- TRAP(50)
+ TRAP(50, cr.ifa)
IVT_END(Reserved_6e00)
IVT_ENTRY(Reserved_6f00, 0x6f00)
- TRAP(51)
+ TRAP(51, cr.ifa)
IVT_END(Reserved_6f00)
IVT_ENTRY(Reserved_7000, 0x7000)
- TRAP(52)
+ TRAP(52, cr.ifa)
IVT_END(Reserved_7000)
IVT_ENTRY(Reserved_7100, 0x7100)
- TRAP(53)
+ TRAP(53, cr.ifa)
IVT_END(Reserved_7100)
IVT_ENTRY(Reserved_7200, 0x7200)
- TRAP(54)
+ TRAP(54, cr.ifa)
IVT_END(Reserved_7200)
IVT_ENTRY(Reserved_7300, 0x7300)
- TRAP(55)
+ TRAP(55, cr.ifa)
IVT_END(Reserved_7300)
IVT_ENTRY(Reserved_7400, 0x7400)
- TRAP(56)
+ TRAP(56, cr.ifa)
IVT_END(Reserved_7400)
IVT_ENTRY(Reserved_7500, 0x7500)
- TRAP(57)
+ TRAP(57, cr.ifa)
IVT_END(Reserved_7500)
IVT_ENTRY(Reserved_7600, 0x7600)
- TRAP(58)
+ TRAP(58, cr.ifa)
IVT_END(Reserved_7600)
IVT_ENTRY(Reserved_7700, 0x7700)
- TRAP(59)
+ TRAP(59, cr.ifa)
IVT_END(Reserved_7700)
IVT_ENTRY(Reserved_7800, 0x7800)
- TRAP(60)
+ TRAP(60, cr.ifa)
IVT_END(Reserved_7800)
IVT_ENTRY(Reserved_7900, 0x7900)
- TRAP(61)
+ TRAP(61, cr.ifa)
IVT_END(Reserved_7900)
IVT_ENTRY(Reserved_7a00, 0x7a00)
- TRAP(62)
+ TRAP(62, cr.ifa)
IVT_END(Reserved_7a00)
IVT_ENTRY(Reserved_7b00, 0x7b00)
- TRAP(63)
+ TRAP(63, cr.ifa)
IVT_END(Reserved_7b00)
IVT_ENTRY(Reserved_7c00, 0x7c00)
- TRAP(64)
+ TRAP(64, cr.ifa)
IVT_END(Reserved_7c00)
IVT_ENTRY(Reserved_7d00, 0x7d00)
- TRAP(65)
+ TRAP(65, cr.ifa)
IVT_END(Reserved_7d00)
IVT_ENTRY(Reserved_7e00, 0x7e00)
- TRAP(66)
+ TRAP(66, cr.ifa)
IVT_END(Reserved_7e00)
IVT_ENTRY(Reserved_7f00, 0x7f00)
- TRAP(67)
+ TRAP(67, cr.ifa)
IVT_END(Reserved_7f00)
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