CFT update day 2
Matthias Haas
freebsd-x11 at mathaas.de
Sun May 29 16:38:00 UTC 2016
Am 29.05.2016 um 16:51 schrieb René Ladan:
> On 23-05-16 10:12, Matthew Macy wrote:
>> The highlights for today are the following:
>>
>> Bug fixes:
>> - Will Andrews fixed attach for some laptops (such as the Carbon X1).
>> The Carbon X1 has a quirky BIOS that doesn't allow the OS to
>> enumerate the GPU's interrupt.
>> - Will Andrews identified a conditionally uninitialized return in
>> idr_find that could lead to a panic in some cases.
>> - Fixed a panic in mtrr_del frequently seen when attach failed.
>> - Sleep/wakeups with interrupts are largely implemented correctly
>> now. Previously a polling 10ms sleep was used. I'm still
>> concerned that the code really needs to be level-triggered.
>>
>> Cleanups:
>> - Logging is now enabled for the first 10s after attach unless
>> dev.drm.drm_debug_keep=1.
>> - Unimplemented warnings are off by default.
>>
> [...snip USB instructions...]
>> If using the github repo, make sure you're using the drm-next-4.6
>> branch.
>>
> I tested the latest github version on my laptop (an Acer Aspire
> E5-773G-78RN with an Intel HD 520 GPU, see [1]), some results:
>
> - xfce4 starts, no visual artifacts
> - XV is disabled but present according to xdpyinfo, i.e. mplayer renders
> movies with black borders in full screen mode
> - glxgears gets up to 30 fps full screen (so something is not accelerated)
> - HDMI output works (when X is started after initially plugging in the
> cable), the TV image keeps getting updated if I close the lid
> - switching back and forth between X and the console works
> - stellarium works
>
> Maybe xf86-video-intel 2.21.15 is missing an PCI id?
It is indeed missing a few PCI ids, I created 2 patches that add those
missing ids, but that doesn't seem to be enough in my case (Iris 550).
You may try them anyway and see if they change anything for you, but I
can't give any support as I'm only a web developer and all this stuff is
not really my area of expertise.
> [1] https://wiki.freebsd.org/Laptops/Acer_Aspire_E5_773G_78RN
>
> Cheers,
> René
>
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-------------- next part --------------
--- src/i915_pciids.h.orig 2013-07-28 15:53:23.000000000 +0200
+++ src/i915_pciids.h 2016-05-23 23:45:14.198344000 +0200
@@ -191,8 +191,8 @@
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
@@ -208,4 +208,134 @@
#define INTEL_VLV_D_IDS(info) \
INTEL_VGA_DEVICE(0x0155, info)
+#define INTEL_BDW_GT12M_IDS(info) \
+ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
+
+#define INTEL_BDW_GT12D_IDS(info) \
+ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+ INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
+ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+
+#define INTEL_BDW_GT3M_IDS(info) \
+ INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x162E, info) /* ULX */
+
+#define INTEL_BDW_GT3D_IDS(info) \
+ INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
+
+#define INTEL_BDW_RSVDM_IDS(info) \
+ INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x163E, info) /* ULX */
+
+#define INTEL_BDW_RSVDD_IDS(info) \
+ INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+ INTEL_BDW_GT12M_IDS(info), \
+ INTEL_BDW_GT3M_IDS(info), \
+ INTEL_BDW_RSVDM_IDS(info)
+
+#define INTEL_BDW_D_IDS(info) \
+ INTEL_BDW_GT12D_IDS(info), \
+ INTEL_BDW_GT3D_IDS(info), \
+ INTEL_BDW_RSVDD_IDS(info)
+
+#define INTEL_CHV_IDS(info) \
+ INTEL_VGA_DEVICE(0x22b0, info), \
+ INTEL_VGA_DEVICE(0x22b1, info), \
+ INTEL_VGA_DEVICE(0x22b2, info), \
+ INTEL_VGA_DEVICE(0x22b3, info)
+
+#define INTEL_SKL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+
+#define INTEL_SKL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
+
+#define INTEL_SKL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+ INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
+
+#define INTEL_SKL_IDS(info) \
+ INTEL_SKL_GT1_IDS(info), \
+ INTEL_SKL_GT2_IDS(info), \
+ INTEL_SKL_GT3_IDS(info), \
+ INTEL_SKL_GT4_IDS(info)
+
+#define INTEL_BXT_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A84, info), \
+ INTEL_VGA_DEVICE(0x1A84, info), \
+ INTEL_VGA_DEVICE(0x1A85, info), \
+ INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
+ INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
+ INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
+
+#define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info)
+
#endif /* _I915_PCIIDS_H */
-------------- next part --------------
--- src/intel_module.c.orig 2013-08-12 18:49:31.000000000 +0200
+++ src/intel_module.c 2016-05-29 18:23:11.975335000 +0200
@@ -108,6 +108,19 @@
.gen = 075,
};
+static const struct intel_device_info intel_broadwell_info = {
+ .gen = 0100,
+};
+
+static const struct intel_device_info intel_cherryview_info = {
+ .gen = 0101,
+};
+
+static const struct intel_device_info intel_skylake_info = {
+ .gen = 0110,
+};
+
+
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -202,6 +215,39 @@
{PCI_CHIP_HASWELL_CRW_E_GT1, "HD Graphics" }, /* ??? */
{PCI_CHIP_HASWELL_CRW_E_GT2, "HD Graphics" }, /* ??? */
{PCI_CHIP_HASWELL_CRW_E_GT3, "Iris(TM) Pro Graphics 5200" },
+ /* Valleyview (Baytail) */
+ {0x0f30, "HD Graphics"},
+ {0x0f31, "HD Graphics"},
+ {0x0f32, "HD Graphics"},
+ {0x0f33, "HD Graphics"},
+ {0x0155, "HD Graphics"},
+ {0x0157, "HD Graphics"},
+
+ /* Broadwell Marketing names */
+ {0x1602, "HD graphics"},
+ {0x1606, "HD graphics"},
+ {0x160B, "HD graphics"},
+ {0x160A, "HD graphics"},
+ {0x160D, "HD graphics"},
+ {0x160E, "HD graphics"},
+ {0x1612, "HD graphics 5600"},
+ {0x1616, "HD graphics 5500"},
+ {0x161B, "HD graphics"},
+ {0x161A, "HD graphics"},
+ {0x161D, "HD graphics"},
+ {0x161E, "HD graphics 5300"},
+ {0x1622, "Iris Pro graphics 6200"},
+ {0x1626, "HD graphics 6000"},
+ {0x162B, "Iris graphics 6100"},
+ {0x162A, "Iris Pro graphics P6300"},
+ {0x162D, "HD graphics"},
+ {0x162E, "HD graphics"},
+ {0x1632, "HD graphics"},
+ {0x1636, "HD graphics"},
+ {0x163B, "HD graphics"},
+ {0x163A, "HD graphics"},
+ {0x163D, "HD graphics"},
+ {0x163E, "HD graphics"},
{-1, NULL}
};
#define NUM_CHIPSETS (sizeof(intel_chipsets) / sizeof(intel_chipsets[0]))
@@ -249,6 +295,14 @@
INTEL_VLV_D_IDS(&intel_valleyview_info),
INTEL_VLV_M_IDS(&intel_valleyview_info),
+ INTEL_BDW_D_IDS(&intel_broadwell_info),
+ INTEL_BDW_M_IDS(&intel_broadwell_info),
+
+ INTEL_CHV_IDS(&intel_cherryview_info),
+
+ INTEL_SKL_IDS(&intel_skylake_info),
+
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
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