Are there SPARC [or other] aligned memory access requirements to avoid exceptions? [now that 11.0's armv6/v7 is allowing more unaligned accesses]

[Ian Lepore]

On Fri, 2016-05-27 at 04:35 -0700, Mark Millard wrote:
> On 2016-May-27, at 12:30 AM, Matthias Andree <matthias.andree at gmx.de>
> wrote:
> 
> > Am 27.05.2016 um 06:14 schrieb Cedric Blancher:
> > > [...]

> The rpi<?> vintage matters:
> 
> Original rpi's (before rpi2): ARM1176JZF-S, 32-bit (not armv6 nor
> armv7-a/cortex-a7)
> 

Original rpi is indeed 1176JZF-S, which IS armv6.  The differences
between it and armv7 are almost entirely in the cache maintenence
routines, and notably not in handling unaligned access the way we now
configure the hardware.  Bottom line:  this is an old slow chip and
you'll be nothing but frustrated using it.

If you're going to get an rpi, get the much faster rpi2, which is a
quad-core system.

These days you may be even better off with something even newer based
on the Allwinner chips (banana pi, cubieboard, a bunch of others),
thanks to the excellent support work done recent (and still happening)
by Jarred and Emmanuel.  But I'm not sure of the price comparisons.

-- Ian