Rearranging kse mailbox

[Daniel Eischen]

On Fri, 18 Jul 2003, Marcel Moolenaar wrote:

> On Fri, Jul 18, 2003 at 03:08:40PM -0700, Julian Elischer wrote:
> > 
> > the ia64 requires that the thread pointer points to 
> > aome location that is 16 bytes long, the first 8 bytes
> > of which is a pointer to the TLS Dynamic thread vector, and the 2nd 8
> > bytes is application specific, but in practice, must be a pointer to
> > the Thread's or KSE's mailbox (I guess KSE to be similar to the others.)
> > 
> > ia32 requires just that the thread control info pointed to by %gs
> > SOMEWHERE contains a pointer to the dtv (where SOMEWHERE is a known
> > offset). (In our case the offset would be 0)
> > 
> > This means that for the UTS to find the active thread under ia64
> > takes an extra level of indirection. (node neither of these
> > affect upcalls as teh UTS upcall target function has the mailbox as an
> > argument and can access it independently of %gs or the tp.
> > 
> > Am I right that "variant 2" (as seen in the ia32 case)
> > applies to allarchitectures other than ia64?
> 
> That is what I need to find out. If the runtime specification has
> a register dedicated for TLS, like on ia64, it will likely behave
> more like ia64 than ia32. I think the amd64 runtime is new enough
> for it to be like ia64.

The amd64 also has a %gs which is used for this.  Only the
kernel can set it, though, so I think it needs to be per-KSE.

> Note that the extra level of indirection on ia64 can be avoided if
> we put the thread control structure at a negative offset from TP.
> The layout would be something like:
> 
> -...              0            8     16      ...+
> [thread structure][DTV pointer][free][static TLS]
> 		  ^
> 		  TP

Can we make this work so that we are not limited to
8192 (or whatever max user LDTs are) threads on i386?

-- 
Dan Eischen