Large number of SATA commits (MFCs) to RELENG_8
Mike Tancsa
mike at sentex.net
Wed Apr 20 23:44:52 UTC 2011
On 4/19/2011 7:50 PM, Jeremy Chadwick wrote:
> I would advocate that folks rebuild world/kernel and make sure there
> aren't any issues seen, or any quirks which were previously needed are
> no longer.
>
> I haven't gone through *all* of the commits yet, but I do see some
> controller-centric things that got MFC'd, such as disabling of NCQ
> support on multiport Marvell 88SX61XX to relieve I/O timeouts when
> doing lots of I/O (common with ZFS).
>
> Below are the commits. Users should absolutely use cvsweb or similar
> tools to examine the commit message and see if anything relevant to
> their storage subsystems was modified.
Remember, this is MFC'd in that it has been in HEAD for some time. Its
not like its all untested. That being said, I tested out an updated
kernel from today on a test box as well as upgraded my home server
<Hitachi HDS721010CLA332 JP4OA3EA> at scbus0 target 0 lun 0 (pass0,ada0)
<Hitachi HDS721010CLA332 JP4OA3EA> at scbus0 target 1 lun 0 (pass1,ada1)
<Hitachi HDS721010CLA332 JP4OA3EA> at scbus0 target 2 lun 0 (pass2,ada2)
<Hitachi HDS721010CLA332 JP4OA3EA> at scbus0 target 3 lun 0 (pass3,ada3)
<Port Multiplier 47261095 1f06> at scbus0 target 15 lun 0 (pass4,pmp0)
<WDC WD1501FASS-00W2B0 01.00101> at scbus4 target 0 lun 0 (pass5,ada4)
<WDC WD1501FASS-00W2B0 01.00101> at scbus6 target 0 lun 0 (pass6,ada5)
# zpool status
pool: test1
state: ONLINE
scrub: none requested
config:
NAME STATE READ WRITE CKSUM
test1 ONLINE 0 0 0
raidz1 ONLINE 0 0 0
ada0 ONLINE 0 0 0
ada1 ONLINE 0 0 0
ada3 ONLINE 0 0 0
label/JP2940HD0352LC ONLINE 0 0 0
errors: No known data errors
all off
siis0 at pci0:1:0:0: class=0x010400 card=0x71321095 chip=0x31321095
rev=0x01 hdr=0x00
vendor = 'Silicon Image Inc (Was: CMD Technology Inc)'
device = 'PCI Express (1x) to 2 Port SATA300 (SiI 3132)'
class = mass storage
subclass = RAID
cap 01[54] = powerspec 2 supports D0 D1 D2 D3 current D0
cap 05[5c] = MSI supports 1 message, 64 bit
cap 10[70] = PCI-Express 1 legacy endpoint max data 128(1024) link
x1(x1)
ecap 0001[100] = AER 1 0 fatal 1 non-fatal 0 corrected
---Mike
--
-------------------
Mike Tancsa, tel +1 519 651 3400
Sentex Communications, mike at sentex.net
Providing Internet services since 1994 www.sentex.net
Cambridge, Ontario Canada http://www.tancsa.com/
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