7.1-STABLE does not boot after recent superpage support MFC

[Alan Cox]

On Fri, Feb 27, 2009 at 10:42 AM, John Baldwin <jhb at freebsd.org> wrote:

> On Friday 27 February 2009 11:21:00 am Michael Butler wrote:
> > John Baldwin wrote:
> > > On Friday 27 February 2009 8:08:30 am Igor Sysoev wrote:
> > >
> > >> And the message is cycled. The kernel does not boot despite
> > >> vm.pmap.pg_ps_enabled value.
> > >
> > > This should now be fixed, apologies for the breakage. :(
> >
> > What are the benefits and/or impacts of enabling this?
> >
> > Is there anything to be gained with respect to cache and/or TLB
> > utilization in allowing entry promotion through a reduced "footprint" or
> > similar? How much does this depend on architecture, say, e.g. Core-2 Duo
> > vs. Pentium?
>
> Yes there are gains due to what you mention, but it does depend on the
> specific processor and specifically the how it manages entries for large
> pages in its TLB (some processsors have separate TLB entries for large
> pages
> and have very few of them, others can store either a small or lage page in
> a
> single TLB slot, etc.).  Alan knows far more of the details of this than I
> do.
>
> > I note that it is not enabled by default in -current either - just
> curious,
>
> Actually, it is enabled by default on amd64 in current.
>
> --
> John Baldwin
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The short answer is ... if you're running an amd64 kernel on a Pentium 4,
Core 2, or tri- or quad-core Opteron/Phenom, enable promotion.  Your results
with other amd64-compatible processors, single- and dual-core Athlon/Opteron
and Atom, will be application dependent.  You'll win some and you'll lose
some.

For a longer answer with data and figures, take a look at this paper:
http://ft.ornl.gov/pubs-archive/ispass-final-csmd.pdf

That said, there are secondary benefits to enabling large page support that
have nothing to do with the TLB, specifically, it makes fork()ing and
exit()ing large address spaces cheaper.

Regards,
Alan