can anyone make available the whole usIII source tree from perforce please

[John Baldwin]

On Monday 23 February 2009 1:15:34 pm Marius Strobl wrote:
> On Mon, Feb 23, 2009 at 09:05:22AM -0500, John Baldwin wrote:
> > On Sunday 22 February 2009 12:02:30 pm Marius Strobl wrote:
> > > On Wed, Feb 18, 2009 at 01:24:00AM +0100, Florian Smeets wrote:
> > > > On 04.02.2009 15:16 Uhr, Craig Butler wrote:
> > > > >Hi Marius,
> > > > >
> > > > >Thanks for all your hard work and pointers so far.  I have compiled 
and
> > > > >installed the new kernel (cas is statically compiled in).  
Unfortunately
> > > > >its panic'ing on boot with the following;
> > > > >
> > > > >cas0:<Sun Cassini+ Gigabit Ethernet>  at device 10.0 on pci0
> > > > >panic: trap: memory address not aligned
> > > > >cpuid = 0
> > > > >Uptime: 1s
> > > > >
> > > > 
> > > > FWIW, i compiled a kernel with these changes and the cards probe fine.
> > > > 
> > > > cas0: <NS DP83065 Saturn Gigabit Ethernet> mem 0x2000000-0x21fffff at 
> > > > device 0.0 on pci1
> > > > miibus1: <MII bus> on cas0
> > > > cas0: 16kB RX FIFO, 9kB TX FIFO
> > > > cas0: Ethernet address: 00:03:ba:XX:XX:XX
> > > > cas0: [ITHREAD]
> > > > cas1: <NS DP83065 Saturn Gigabit Ethernet> mem 0x2400000-0x25fffff at 
> > > > device 1.0 on pci1
> > > > miibus2: <MII bus> on cas1
> > > > cas1: 16kB RX FIFO, 9kB TX FIFO
> > > > cas1: Ethernet address: 00:03:ba:XX:XX:XX
> > > > cas1: [ITHREAD]
> > > > 
> > > > I don't have a cable connected yet, as the machine is remote, but I'll 
> > > > be sure to test it soon.
> > > > 
> > > 
> > > FYI, the above panic likely isn't a problem of cas(4) but
> > > arises from the fact that the resource of that NIC starts
> > > at 0 according to its BAR, which is somewhat uncommon but
> > > nevertheless should work yet seems to trigger a bug at
> > > some other level.
> > 
> > The PCI bus driver assumes a BAR of 0 is an invalid resource.  There are 
many 
> > systems that use 0 to disable a BAR.  I have no idea if "0" is a magic 
value 
> > to disable an individual BAR in the PCI spec itself, however.
> > 
> 
> I'm aware of the former, my understanding of the pci(4) code
> is that it won't pre-allocate such a resource but modulo bugs
> treats it normally when a driver allocates it though.

No, what will happen is that we don't create a resource list entry for it 
since it is zero.  Then, when pci_alloc_resource() is called, it will see 
that there isn't a resource list entry and will attempt to allocate a fresh 
resource range for the BAR and assign it to the BAR.  Perhaps we need to have 
some var in <machine/_param.h> to indicate if 0 is a valid BAR address or 
not.  Also, see pci_delete_resource() which assumes it can completely wipe a 
BAR by writing 0 to it.  But you would need to patch pci_add_map() in a 
couple of places where it is testing base == 0 to basically ignore those 
tests to get it to use the 0 - N range.

-- 
John Baldwin