Intel hardware bug

[Cy Schubert]

SPARC definitely does out of order execution.

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Sent using a tiny phone keyboard.
Apologies for any typos and autocorrect.
Also, this old phone only supports top post. Apologies.

Cy Schubert
<Cy.Schubert at cschubert.com> or <cy at freebsd.org>
The need of the many outweighs the greed of the few.
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-----Original Message-----
From: Eric McCorkle
Sent: 05/01/2018 10:45
To: freebsd-security at freebsd.org
Subject: Re: Intel hardware bug

On 01/05/2018 11:40, Nathan Whitehorn wrote:

> POWER has the same thing. It's actually stronger separation, since user
> processes don't share addresses either -- all processes, including the
> kernel, have windowed access to an 80-bit address space, so no process
> can even describe an address in another process's address space. There
> are ways, of course, in which IBM could have messed up the
> implementation, so the fact that it *should* be secure does not mean it
> *is*.

That's interesting, as it conflicts with Red Hat's vulnerability
disclosure.  It that because the silicon is buggy, or because Linux
somehow ends up being vulnerable when it need not be?

> 
> SPARC avoids the issue because almost all implementations are in-order.

Definitely not true of the post-Oracle models.  I saw a tech talk on the
core once.
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