How FreeBSD manage more than 4GB on 32 bits architecture
Pierre-Yves.Peneau at lip6.fr
Fri Apr 10 09:17:21 UTC 2015
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On 04/10/2015 01:04 AM, Lowell Gilbert wrote:
> Pierre-Yves Péneau <Pierre-Yves.Peneau at lip6.fr> writes:
>> I did not want give too much details in my first email to avoid
>> confusion, but this is exactly what I bring.. So let's be more
>> clear :-)
>> I'm working on an European project called TSAR(*). This project
>> aims to create a TeraScale ARchitecture with low consumption.
>> That's why 32 bits processors were chosen. Our architecture is
>> cc-NUMA. We have 256 clusters (maximum). Each cluster contains 4
>> processors and have 4GB of RAM. MMUs can translate 32 bits
>> virtual addresses into 40 bits physical addresses using two
>> coordinates, which are used to identify each cluster. These
>> coordinates are on 4 bits, each. So, a physical address is build
>> like this:
>> | X coord(4 bits) | Y coord (4 bits) | Vaddr (32 bits) |
>> That's how we obtain 40 bits of addressable space, and why we
>> have 1TB of physical memory.
>> So, I've the required hardware I think. My problem is to find
>> out how FreeBSD can use this mechanisms. But I'm realizing that
>> it may be not a kernel issue, because it's an hardware
>> functionality which should works with Linux too. Right ?
> That is a bit of an oversimplification. The quote that led you to
> make your original post indicates a problem with the Linux mapping
> model which would not apply to using FreeBSD on your architecture.
That's exactly what I thought, but that's your documentation which led
me to this conclusion. The "Unlike Linux" part confused me. I thought
that FreeBSD had a better physical memory management than Linux (maybe,
but not for what I'm looking for).
I think you should add something concerning the page table size, like
you said in your previous email. That's the answer I was looking for,
and it may be useful for those who have the same question (even if
nobody in the world except me is trying to deal with 1TB and 32 RISC
> That's relatively minor, though. Your architecture has its own page
> table design, which makes sense to me on its own, but I don't have
> a sense of how much space the page table itself will take up.
> Obviously a page table for 1TB of 4KB pages is already too big for
> a 32-bit address space, even before you try mapping in the actual
> pages. So the page sizes will clearly average out much larger.
> My guess would be that the key design issue for you will be how
> your project's page table model fits into the interface of each
> OS's VM system. I can't give much advice in that area, though -- I
> tend to deal with embedded systems, which have entirely separate
> sets of challenges.
> Best wishes. _______________________________________________
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