Per core frequency control

Chuck Swiger cswiger at
Tue Nov 9 19:52:06 UTC 2010

On Nov 9, 2010, at 9:54 AM, David Brodbeck wrote:
> On Tue, Nov 9, 2010 at 5:17 AM, Svein Skogen (Listmail account)
> <svein-listmail at> wrote:
>> You did read the "symmetric" part of "symmetric multi processor" didn't you?
>> It's a limitation of the technology. One clock.
> I don't think that's quite true.  The newer Intel server chipsets have
> the ability to throttle back idle cores and boost the speed of active
> ones, to improve performance on single-threaded workloads.

You're talking about:

In point of fact, what this is doing is that the CPU is adjusting it's own multipliers of Bclk (normally 133.33 MHz, although 160MHz can also used if XMP profile timing is active) if it can halt or put to sleep some of the cores into C1/C1E/C3 states.

There still is only one base clock frequency being provided to all of the cores, and the ones which are still awake will still all be running at the same speed. [1]


[1] Modulo extreme thermal conditions involving TM1 but not TM2; TM1 thresholds are per-CPU.

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