pefo at opsycon.se
Wed Jun 14 09:17:38 UTC 2006
On Wednesday 14 June 2006 00:50, Johnny Billquist wrote:
> Per Fogelstrvm wrote:
> > On Tuesday 13 June 2006 14:23, Rick Kelly wrote:
> >>Johnny Billquist said:
> >>>>There's actually a cheesy way to do demand paging with microprocessors
> >>>>that don't support demand paging (such as the original 68000--another
> >>>>"16 bit" machine). The way to do this is to run two processors in
> >>>>parallel but skewed by one instruction. If the first one does a bad
> >>>>memory fetch, then the second one will not have fetched the instruction
> >>>>causing the fault so contains restartable machine state. Masscomp sold
> >>>>a machine like this once.
> >>>Didn't the first Apollos do this?
> >>And also the Sun 1.
> > IIRC it was simpler than that. When the first cpu caused a 'miss' it was
> > put in wait and cpu 2 handled the pagein and then released cpu 1. Keeping
> > the two cpus synched, one instruction apart would have been too
> > complicated if not impossible...
> Your idea will not work, as far as I can tell.
Well it does. You are making assumptions which causes it to now work.
As Marcus already explained, the CPU is not allowed to trap but kept
waiting for the data. This of course had a terrible performance impact
(if you were running many background jobs) but considering that the Apollo
Domain stations were mostly used for CAD with huge data requirements it was
not a bad thing though. At that time RAM was very expensive and top notch
performance was not a very big issue at all times. And the MMU chip was a
piece of crap and expensive so most companies built their own MMU, like we
did. Actually we never used any of Motorolas MMU chips in any of our systems.
> If the first CPU instruction execution causes a miss, the end result in
> the CPU will be pretty undefined, and you cannot restart. That's the
> whole point in why you'd have a second CPU shadowing the first one. So
> that you'd be able to restore the state as it were before the illegal
> memory access.
> And that was the problem with the original 68000. On an illegal memory
> reference, you would not know what state the CPU was in before the
> instruction, so you could not back it up, and re-execute the instruction
> after a page fault.
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