jd10008 at yahoo.com
Tue Aug 19 16:21:39 PDT 2003
Som question on FreeBSD 5.x SMP Synchronization:
On motherboards with 2-4 cpus (such as those from
and Supermicro and others), what is the
chip part called? How can I determine if it is
present or not?
If the MP motherboard does not have hardware cache
what does the FreeBSD kernel resort to?
On old SMP HW architectures, a cross-processor
was used to purge local cpu caches such that the
would wait for all other cpu's to rendezvous to a
before the issuing cpu would proceed to try to lock
lock. All that, because of lack of cache snooping
Does FreeBSD employ priority inheritance to address
3. Is there a quantification of the current SMP
I have more questions about the FreeBSD 5.x kernel,
but will send them another time.
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