powerpc: should the tlbie routine have a isync after the last ptesync? (also MPC750 notes)

[Mark Millard]

From: PPC_Vers201_Book3_public.pdf and its "Page Table
Update Synchronization Requirements" section. . .

QUOTE
As noted in the description of the Synchronize instruction in Book II, address translation associated with instructions which occur in program order subsequent to the Synchronize (and this includes the ptesync variant) may actually be performed prior to the completion of the Synchronize. To ensure that these instructions and data which may have been speculatively fetched are discarded, a context synchronizing operation is required.
END QUOTE

That leave me wondering if there should be a isync
just before the mtx_unlock_spin statement in:

static void
tlbie(vm_offset_t va)
{
 
        mtx_lock_spin(&tlbie_mtx);
        __asm __volatile("ptesync");
        __asm __volatile("tlbie %0" :: "r"(va));
        __asm __volatile("eieio; tlbsync; ptesync");
        mtx_unlock_spin(&tlbie_mtx);
}



MPC750 specific notes in-part associated with tlbie
routine and the likes of ptesync :

For the MPC750 in the iMac G3 I've found no evidence that
ptesync (sync with L=2 in more modern terms) is defined.
It might no-op for all I can tell. Or be just like
sync (with L=0) on the MPC750.

lwsync (sync with L=1) has the same sort of status:
undefined as far as I can tell.

I've been looking in MPC750UM.pdf . It has some description
of the likes of isync and such. It it indicates sync is
just the reserved pattern that effectively says L=0 in
more modern terms.

So Im unclear if the ptesync and lwsync types of instructions
should be sync instructions for any potential MPC750 support.

I'm unsure if FreeBSD is still intending that it is
coded such that MPC750 (and, so, iMac G3's) should still
operate okay. (There may be more than ptesync and lwsync
use at issue.)


===
Mark Millard
marklmi at yahoo.com
( dsl-only.net went
away in early 2018-Mar)