[Bug 205458] 11.0-CURRENT/10-STABLE powerpc64: a PowerMac G5 specific sys/powerpc/ofw/ofw_machdep.c change for reliable PowerMac G5 booting (with lots of RAM)

[Jukka A. Ukkonen]

On 09/14/16 17:17, Nathan Whitehorn wrote:
> 
> On 09/14/16 00:57, Jukka A. Ukkonen wrote:
>> On 09/13/16 20:28, Nathan Whitehorn wrote:
>>> Maybe firmware needs SPRG1-3 restored? Any chance you could try deleting
>>> the mtsprg1-3 one-by-one?
>>> -Nathan
>> But of course. It will take some time, though.
>> Is there any particular order I should try them?
>> 1, 2, and 3?
>> I mean you and Mark obviously have a lot better
>> understanding about ppc and what to expect when
>> one touches sprg#. I will be flying pretty much
>> blindfolded.
>>
>> --jau
>>
> 
> I'm flying blind here too. It's one of SPRG1 or SPRG3 that I expect
> firmware needs restored on your system. SPRG2 is obliterated by the SLB
> fault handler, so if firmware needs it, we can't provide it anyway. And
> we know it doesn't need SPRG0 since Mark's patch works for you.
> -Nathan


Right, it seems my PowerMac G5 is perfectly happy with this...

        __asm __volatile("mfsprg0 %0\n\t"
                         : "=&r"(ofw_sprg0_save)
                         :
                         );

This does not seem all unexpected when I read the hardware
specification for these registers. See the attachment.
In case OFW does some extra magic with these registers,
I might be running a fault prone setup at the moment, but
for now there have been no symptoms of anything going
seriously wrong.

--jau

-------------- next part --------------
SPRG0 - SPRG3 are 64-bit or 32-bit registers,
depending on the type of PowerPC processor.
They are provided for general operating system use,
such as performing a fast state save or for
supporting multiprocessor implementations

Table 2-19. Conventional Uses of SPRG0 - SPRG3

Register 	Description

SPRG0		Software may load a unique physical address in this
		register to identify an area of memory reserved for
		use by the first-level exception handler.
		This area must be unique for each processor in the system.

SPRG1		This register may be used as a scratch register by
		the first-level exception handler to save the content
		of a GPR. That GPR then can be loaded from SPRG0 and
		used as a base register to save other GPRs to memory.

SPRG2		This register may be used by the operating system as needed.

SPRG3		This register may be used by the operating system as needed.