[Bug 227591] [NEW PORT] devel/yosys - Verilog RTL syntensis

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Wed May 16 08:17:45 UTC 2018

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227591

--- Comment #1 from Tobias Kortkamp <tobik at freebsd.org> ---
See https://forums.freebsd.org/threads/new-ports-lattice-fpga-tools.65552/ for
some feedback.

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